SLVUD67 September   2025 TPS6521505-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4TPS65215 with TPS65219EVM
  8. 5Programming Instructions
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring GPIOs
    5. 5.5  Configuring Sequence
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 NVM Re-Programming
  9.   A Non-NVM Registers
  10.   B Loading a NVM Configuration File to PMIC
  11.   C PMIC Configurable Fields
  12.   References
  13.   E Revision History

5.5 Configuring Sequence

The process to configure the PMIC sequence consist of the following two steps:

  1. Power-up/Power-down slot assignment: The slot assignment defines the order in which rails turn ON or OFF. Each of the PMIC rails must have a slot assigned. There are 16 slots available (0-15). Multiple rails (including GPIOs) can be assigned to the same slot so they be enabled at the same time.
  2. Power-up/Power-down slot duration: The slot duration is the timing between the start of one slot to the start of the next slot. For example, if Buck1 is assigned to slot0 with a 3ms duration and Buck2 is assigned to slot 1, then Buck2 turns ON 3ms after Buck1.

Note: The slot duration does not dictate how long it takes for the rails to ramp. The slot duration only specifies how long the PMIC waits before enabling (or disabling) the rails that were assigned to the next slot.
Power Up Sequence Configuration Figure 5-6 Power Up Sequence Configuration
Power Down Sequence Configuration Figure 5-7 Power Down Sequence Configuration
Table 5-10 Power-Up Sequence - Slot Assignments
Register Address Bit Field Name Settings
Power-up Sequence
Slot Assignment		 0x11 7-4 BUCK1_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0x10 7-4 BUCK2_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0xF 7-4 BUCK3_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0xE 7-4 LDO1_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0xC 7-4 LDO2_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0x15 7-4 GPO1_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0x14 7-4 GPO2_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0x13 7-4 GPIO_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
0x12 7-4 nRST_SEQUENCE_ON_SLOT See the register map on the device-specific data sheet.
Table 5-11 Power-Up Sequence - Slot Duration
Register Address Bit Field Name Settings
Power-up Sequence
Slot Duration		 0x16 7-6 POWER_UP_SLOT_0_DURATION See the register map on the device-specific data sheet.
5-4 POWER_UP_SLOT_1_DURATION See the register map on the device-specific data sheet.
3-2 POWER_UP_SLOT_2_DURATION See the register map on the device-specific data sheet.
1-0 POWER_UP_SLOT_3_DURATION See the register map on the device-specific data sheet.
0x17 7-6 POWER_UP_SLOT_4_DURATION See the register map on the device-specific data sheet.
5-4 POWER_UP_SLOT_5_DURATION See the register map on the device-specific data sheet.
3-2 POWER_UP_SLOT_6_DURATION See the register map on the device-specific data sheet.
1-0 POWER_UP_SLOT_7_DURATION See the register map on the device-specific data sheet.
0x18 7-6 POWER_UP_SLOT_8_DURATION See the register map on the device-specific data sheet.
5-4 POWER_UP_SLOT_9_DURATION See the register map on the device-specific data sheet.
3-2 POWER_UP_SLOT_10_DURATION See the register map on the device-specific data sheet.
1-0 POWER_UP_SLOT_11_DURATION See the register map on the device-specific data sheet.
0x19 7-6 POWER_UP_SLOT_12_DURATION See the register map on the device-specific data sheet.
5-4 POWER_UP_SLOT_13_DURATION See the register map on the device-specific data sheet.
3-2 POWER_UP_SLOT_14_DURATION See the register map on the device-specific data sheet.
1-0 POWER_UP_SLOT_15_DURATION See the register map on the device-specific data sheet.
Table 5-12 Power-Down Sequence - Slot Assignments
Register Address Bit Field Name Settings
Power-down Sequence
Slot Assignment		 0x11 7-4 BUCK1_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0x10 7-4 BUCK2_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0xF 7-4 BUCK3_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0xE 7-4 LDO1_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0xC 7-4 LDO2_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0x15 7-4 GPO1_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0x14 7-4 GPO2_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0x13 7-4 GPIO_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
0x12 7-4 nRST_SEQUENCE_OFF_SLOT See the register map on the device-specific data sheet.
Table 5-13 Power-Down Sequence - Slot Duration
Register Address Bit Field Name Settings
Power-down Sequence
Slot Duration		 0x1A 7-6 POWER_DOWN_SLOT_0_DURATION See the register map on the device-specific data sheet.
5-4 POWER_DOWN_SLOT_1_DURATION See the register map on the device-specific data sheet.
3-2 POWER_DOWN_SLOT_2_DURATION See the register map on the device-specific data sheet.
1-0 POWER_DOWN_SLOT_3_DURATION See the register map on the device-specific data sheet.
0x1B 7-6 POWER_DOWN_SLOT_4_DURATION See the register map on the device-specific data sheet.
5-4 POWER_DOWN_SLOT_5_DURATION See the register map on the device-specific data sheet.
3-2 POWER_DOWN_SLOT_6_DURATION See the register map on the device-specific data sheet.
1-0 POWER_DOWN_SLOT_7_DURATION See the register map on the device-specific data sheet.
0x1C 7-6 POWER_DOWN_SLOT_8_DURATION See the register map on the device-specific data sheet.
5-4 POWER_DOWN_SLOT_9_DURATION See the register map on the device-specific data sheet.
3-2 POWER_DOWN_SLOT_10_DURATION See the register map on the device-specific data sheet.
1-0 POWER_DOWN_SLOT_11_DURATION See the register map on the device-specific data sheet.
0x1D 7-6 POWER_DOWN_SLOT_12_DURATION See the register map on the device-specific data sheet.
5-4 POWER_DOWN_SLOT_13_DURATION See the register map on the device-specific data sheet.
3-2 POWER_DOWN_SLOT_14_DURATION See the register map on the device-specific data sheet.
1-0 POWER_DOWN_SLOT_15_DURATION See the register map on the device-specific data sheet.