SLVUD67 September   2025 TPS6521505-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4TPS65215 with TPS65219EVM
  8. 5Programming Instructions
    1. 5.1  Configuring Enable Settings
    2. 5.2  Configuring the Bucks
    3. 5.3  Configuring LDOs
    4. 5.4  Configuring GPIOs
    5. 5.5  Configuring Sequence
    6. 5.6  Configuring Multi-Function Pins
    7. 5.7  Configuring the EN/PB/VSENSE Pin
    8. 5.8  Changing I2C Address
    9. 5.9  Configuring Mask Settings
    10. 5.10 NVM Re-Programming
  9.   A Non-NVM Registers
  10.   B Loading a NVM Configuration File to PMIC
  11.   C PMIC Configurable Fields
  12.   References
  13.   E Revision History

5.3 Configuring LDOs

There are several settings that can be programmed for the LDO regulators. These include the output voltages, and under voltage (UV) monitoring among others.

  • Figure 5-4 shows the settings to be changed when using the TPS65215-GUI.
  • Table 5-6 and Table 5-7 show the register fields to be written when NOT using the TPS65215-GUI.
LDOs Settings Using the TPS65215-GUI Figure 5-4 LDOs Settings Using the TPS65215-GUI
Table 5-6 NVM Registers for LDO1 Settings
Register Address Bit Field Name Settings
Output Voltage 0x07 5-0 LDO1_VSET See the register map on the device-specific data sheet.
Configuration 7 LDO1_LSW_CONFIG 0h = LDO1 NOT configured as load-switch
1h = LDO1 configured as Load-switch
6 LDO1_BYP_CONFIG 0h = LDO1 configured as LDO
1h = LDO1 configured as Bypass
(only applicable if LDO1_LSW_CONFIG 0x0)
UV monitoring 0x1E 3 LDO1_UV_THR 0h = -5% UV
1h = -10% UV
Table 5-7 NVM Registers for LDO2 Settings
Register Address Bit Field Name Settings
Output Voltage 0x05 5-0 LDO2_VSET See the register map on the device-specific data sheet.
Configuration 6 LDO2_LSW_CONFIG 0h = LDO Mode
1h = LSW Mode
Ramp 7 LDO2_SLOW_PU_RAMP 0h = Fast ramp for power-up
1h = Slow ramp for power-up
UV Monitoring 0x1E 5 LDO2_UV_THR 0h = -5% UV
1h = -10% UV