SLVUDA2 July   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  9. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Test Points
    3. 2.3 Setup
      1. 2.3.1 Reference Voltage
        1. 2.3.1.1 Configuration 1: REFA and REFB = GND
        2. 2.3.1.2 Configuration 2: OPA CH A Bias REFA and REFB
        3. 2.3.1.3 Configuration 3: REFA and REFB Bias Independently
      2. 2.3.2 Current Sensing
      3. 2.3.3 Input Filtering
      4. 2.3.4 Output Load
    4. 2.4 Best Practices
  10. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  11. 4Additional Information
    1. 4.1 Trademarks
    2. 4.2 Related Documentation

Power Requirements

The INA1H94 operates on a power supply voltage range from ±2V to ±9V dual supply or 4V to 18V single supply. The device can be operated in dual or single supply. The EVM has connections for positive supply (V+), negative supply (V−), and ground (GND) as shown in Figure 2-1. Bypass capacitors are populated on the board (C1, C2, C11, C12) for the device supply. The supply connection can be done either using a standard 4mm banana jack or using the power supply test points, both are not required for operation. If using in single supply, connect both (V−) and GND to ground.

INA1H94EVM Power Connectors and Test
                    Points Figure 2-1 Power Connectors and Test Points

Figure 2-2 shows the high voltage section on the board is denoted by the silkscreen and the high voltage-rated banana jack connectors (J5, J7). The silkscreen portion is to show where the PCB traces have been optimized for high voltage clearance and design rules to withstand the max voltage rating of ±150V per device rating. All other banana jack connectors are rated for less than 50V.

INA1H94EVM High Voltage Section of
                    Evaluation Board Figure 2-2 High Voltage Section of Evaluation Board

When using an external reference buffer, the supply voltage for the reference buffer (REFV+ and REFV−) can be either tied to the board supply (V+ and V− or GND) via J10 and J11 or connected externally by the test points TP13 and TP10, both are not required for operation. Location of the test points and headers are indicated in Figure 2-3. If REFV+ and REFV− are driven externally, remove shunts from J10 and J11. Do not connect the board supplies (V+ and V−) and REF supplies (REFV+ and REFV−) together if driving externally. See Table 2-1 for more information.

INA1H94EVM Reference Power Pin Headers
                    and Test Points Figure 2-3 Reference Power Pin Headers and Test Points
Table 2-1 Reference Buffer Supply Voltage Headers
HEADER NAME FUNCTION SETTING DESCRIPTION
J10 REFV+ Closed REFV+ is shorted to V+. Do not apply an external voltage to TP13
Open REFV+ is floating and must be biased externally with TP13
J11 REFV- Closed (REFV− to V−) REFV− is shorted to V−. Do not apply an external voltage to TP10
Closed (REFV− to GND) REFV− is shorted to GND. Do not apply an external voltage to TP13
Open REFV− is floating and must be biased externally with TP10