SNAS880A December   2024  – October 2025 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.2.3 Spread-Spectrum Clocking

FOD0 supports spread-spectrum clocking (SSC). SSC can be used to reduce peak radiated emissions by modulating the output frequency. When SSC_EN (R4[0]) = '1', any outputs that are sourced from FOD0 have SSC. SSC_MOD_TYPE (R4[1]) selects between down-spread modulation (SSC_MOD_TYPE = 0) or center-spread modulation (SSC_MOD_TYPE = 1). The LMK3C0105 has four built-in down-spread SSC options, as well as a custom SSC option. SSC_CONFIG_SEL (R9[11:9]) selects between the custom or preconfigured options. The preconfigured options are optimized for a 200MHz output from FOD0. Table 7-4 details the register settings for the preconfigured SSC options.

Table 7-4 Predefined SSC Configurations
SSC_CONFIG_SELDown-spread SSC Depth
0x0Custom, based on SSC_STEPS and SSC_STEP_SIZE
0x1–0.10%
0x2–0.25%
0x3–0.30%
0x4–0.50%
All other valuesReserved

If Custom SSC is selected, then SSC_STEPS (R4[14:2]) and SSC_STEP_SIZE (R5) must be configured to set the modulation depth. Use Equation 5 or Equation 6 to determine the SSC_STEPS (R4[14:2]) register settings, and use Equation 7 or Equation 8 to determine the SSC_STEP_SIZE (R5) settings. Equation 7 is for down-spread SSC and Equation 8 is for center-spread SSC.

Equation 5. D o w n - s p r e a d :   S S C _ S T E P S   =   i n t F F O D 0 F M O D ÷ 2
Equation 6. C e n t e r - s p r e a d :   S S C _ S T E P S =   i n t F F O D 0 F M O D ÷ 4

where:

  • FFOD0: FOD0 Frequency
  • FMOD: Modulation frequency, typically 31.5kHz is used

Equation 7. S S C _ S T E P _ S I Z E   =   f l o o r F B A W F F O D 0 ×   1 1 – S S C _ D E P T H – 1 S S C _ S T E P S   ×   D E N  
Equation 8. S S C _ S T E P _ S I Z E   =   f l o o r F B A W F F O D ×   1 1 – S S C _ D E P T H – 1 1 + S S C _ D E P T H 2 × S S C _ S T E P S   ×   D E N

where:

  • SSC_STEP_SIZE: Numerator increment value per step for SSC
  • FBAW: BAW frequency, 2467MHz. Note that the FBAW value varies from device to device.
  • SSC_DEPTH: Modulation depth, expressed as a positive value. If –0.5% depth is used, this value is 0.005
  • SSC_STEPS: Result from Equation 5 for down-spread or Equation 6 for center-spread
  • DEN: Fractional denominator, 224

If using a mix of SSC on one output and no SSC on a different output, there can be crosstalk between the two outputs. Contact TI to request measurement data for a specific configuration when configuring SSC on only a single output.

When modifying the SSC settings, do not set SSC_EN to a '1' until the other SSC settings have been configured. Perform the following steps for configuring the SSC:

  1. Set PDN to a '1'.
  2. Set OTP_AUTOLOAD_DIS to a '1'.
  3. Modify SSC_MOD_TYPE, SSC_STEP_SIZE, and SSC_STEPS as necessary.
  4. Set SSC_EN to a '1'.
  5. Set PDN to a '0'.