SNAS880A December   2024  – October 2025 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

VDD = VDDO = 1.8V, 2.5V or 3.3V ± 5%, TA = TA,min to TA,max
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY STABILITY
∆ftotal Total frequency stability All factors included: temperature variation, 10-year aging, solder shift, hysteresis and initial frequency accuracy –25 25 ppm
LVCMOS CLOCK OUTPUT CHARACTERISTICS
fout Output frequency 2.5 200 MHz
dV/dt Output slew rate VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load 2.6 4.7 V/ns
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load 2.6 3.7 V/ns
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load 1.5 3.2 V/ns
VOH Output high voltage IOH = –15mA at 3.3V 0.8 × VDDO VDDO V
IOH = –12mA at 2.5V
IOH = –8mA at 1.8V
VOL Output low voltage IOL = 15mA at 3.3V 0.4 V
IOL = 12mA at 2.5V
IOL = 8mA at 1.8V
Ileak Output leakage current Output tri-stated. VDD = VDDO = 3.465V –5 0 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25MHz 45 55 %
fout > 156.25MHz 40 60 %
tskew Output-to-output skew Same FOD, LVCMOS output 50 ps
Cload Maximum load capacitance 15 pF
LVCMOS REFCLK CHARATERISTICS
fout Output frequency See(1) 12.5(2) 200 MHz
dV/dt Output slew rate VDDO = 3.3V ± 5%, measured from 20% to 80%, 4.7pF load(1) 2.6 6.7 V/ns
VDDO = 2.5V ± 5%, measured from 20% to 80%, 4.7pF load(1)(4) 1.8 4.5 V/ns
VDDO = 1.8V ± 5%, measured from 20% to 80%, 4.7pF load(1)(4) 1 3.2 V/ns
Ileak Output leakage current Output tri-stated. VDD = VDDO = 3.465V(1)(4) –5 5 µA
Rout Output impedance 17 Ω
ODC Output duty cycle fout ≤ 156.25MHz(1) 45 55 %
ODC Output duty cycle fout > 156.25MHz(1) 40 60 %
Cload Maximum load capacitance See(1) 15 pF
RJ Random jitter 12kHz to 20MHz integrated jitter at 50MHz(1) 0.5 ps
SSC CHARACTERISTICS
fout Output frequency range that supports SSC (any output format) 2.5 200 MHz
fSSC SSC modulation frequency 30 31.5 33 kHz
fSSC-deviation SSC deviation (modulation depth) Down spread (programmable) –3 –0.1 %
Center spread (programmable) ±0.05 ±1.5 %
fSSC-deviation-accuracy SSC deviation accuracy fout ≤ 100MHz, down spread 0 0.01 %
100MHz < fout ≤ 200MHz, down spread 0 0.05 %
fout ≤ 100MHz, center spread 0 0.01 %
100MHz < fout ≤ 200MHz, center spread 0 0.05 %
df/dt max SSC frequency slew rate 0 < fSSC-deviation ≤ –0.5% 1250 ppm/µs
TIMING CHARACTERISTICS
tstartup Start-up time VDD = 2.5V or 3.3V. Time elapsed from all VDD pins reach 2.1V until first output clock rising edge. Output clock is always within specification 1 ms
VDD = 1.8V. Time elapsed from all VDD pins reach 1.6V until first output clock rising edge. Output clock is always within specification 1.5 ms
tOE Output enable time.  After CLOCK_READY status is '1', time elapsed between OE assertion and first output clock rising edge. Output is not tristated when disabled. 7 output clock cycles
tOD Output disable time.  Time elapsed between OE deassertion and last output clock falling edge. 7 output clock cycles
POWER CONSUMPTION CHARACTERISTICS
IDD Core supply current, not including output drivers One FOD enabled, 100MHz ≤ fFOD ≤ 200MHz 57.5 79.9 mA
One FOD enabled, 200MHz < fFOD ≤ 400MHz 67 90.7 mA
Two FODs enabled, 100MHz ≤ fFOD ≤ 200MHz 81.1 105.8 mA
Two FODs enabled, 200MHz < fFOD ≤ 400MHz 97.8 125.8 mA
IDDO Output supply current, per output channel 1.8V LVCMOS. fout = 50MHz(3) 4.2 5 mA
1.8V LVCMOS. fout = 200MHz(3) 11.7 13.4 mA
2.5V LVCMOS. fout = 50MHz(3) 5.6 6.4 mA
2.5V LVCMOS. fout = 200MHz(3) 15.3 17.3 mA
3.3V LVCMOS. fout = 50MHz(3) 6.8 7.7 mA
3.3V LVCMOS. fout = 200MHz(3) 19.2 21.7 mA
IDDREF REFCLK supply current 1.8V LVCMOS. fout = 50MHz(3) 3.4 3.9 mA
1.8V LVCMOS. fout = 200MHz(3) 9.5 11.7 mA
2.5V LVCMOS. fout = 50MHz(3) 4.7 5.3 mA
2.5V LVCMOS. fout = 200MHz(3) 12.8 15.8 mA
3.3V LVCMOS. fout = 50MHz(3) 5.9 6.6 mA
3.3V LVCMOS. fout = 200MHz(3) 16.6 20.2 mA
PSNR CHARACTERISTICS
PSNRLVCMOS Power Supply Noise Rejection for LVCMOS outputs(4) 10kHz –76.7 -58.1 dBc
50kHz –80.9 -57.9 dBc
100kHz –81.8 -57 dBc
500kHz –84.3 -61.7 dBc
1MHz –97.6 -78.1 dBc
5MHz –104.3 -79 dBc
10MHz –108.7 -89.5 dBc
2-STATE LOGIC INPUT CHARACTERISTICS
VIH-Pin2 Input high voltage for Pin 2 0.7 × VDD VDD + 0.3 V
VIL-Pin2 Input low voltage for Pin 2 GND – 0.3 0.3 × VDD V
VIH-Pin1 Input high voltage for Pin 1 1.15 VDD + 0.3 V
VIL-Pin1 Input low voltage for Pin 1 –0.3 0.65 V
VIH-Pin3,4 Input voltage high for OTP_SEL[1:0] 0.7 × VDD VDD + 0.3 V
VIL-Pin3,4 Input voltage low for OTP_SEL[1:0] GND - 0.3 0.8 V
VIH-Pin15 Input voltage high for Pin 15 0.65 × VDD VDD + 0.3 V
VIL-Pin15 Input voltage low for Pin 15 –0.3 0.4 V
Rext-up/down-Pin1,2 Recommended external pullup or pulldown resistor for Pin 1, 2 0 1 10 kΩ
Rext-up/down-Pin3,4,15 Recommended external pullup or pulldown resistor for Pin 3, 4, 15 0 10 60 kΩ
tR/tF OE signal rise or fall time 10 ns
Cin Input capacitance 3 pF
(1) Tested with 10kΩ external pullup or pulldown resistor
(2) REFCLK can be /2, /4, /8 from either FOD0 or FOD1. Both FODs support 100MHz to 400MHz.
(3) 4.7pF capacitive load with a 5in trace
(4) All power supply pins are tied together. 0.1µF capacitor placed close to each power supply pin. Apply 50mVpp ripple and measure the spur level at the clock output