8 Clock Distribution in MicroTCA Systems

MicroTCA standard provides a modular, open platform for Low to Mid-range telecom and datacom equipment with capacity of up to 144 Gbps. MircoTCA systems are optimized for smaller physical sizes and more cost sensitive applications.

Similar to the ATCA standard, the MicroTCA (uTCA) standard also specifies the use of M-LVDS technology for clock distribution networks. The MicroTCA specification (PICMG MTCA.0) defines non-redundant and redundant clocking architectures. The non-redundant clocking architecture is for systems with a single MicroTCA Carrier Hub (MCH). This architecture allows up to three point-to-point links per Advanced Mezzanine Card (AMC) and up to 36 links per MCH. Figure 8-1 shows a single point-to-point clock link between a MCH and AMC in a non-redundant backplane. Note that the clock bus is terminated on the backplane at the MCH card and on the AMC card. In point-to-point links, M-LVDS device transmit clock signals with maximum noise margin.

Figure 8-1 MicroTCA Non-redundant Clock Distribution Interface Example

The redundant clock architecture is for dual MCH systems that operate in a redundant manner. In this clock architecture, each MCH connects to each AMC with a point-to-point link as in Figure 8-1. However, the connection between an AMC to each of the MCH cards is implemented with a multipoint network as illustrated in Figure 8-2. The effects of unterminated stubs in this multipoint topology variant are minimized with the use of series resistors. The controlled signal edges of M-LVDS devices further aid in distributing clocks to all cards within a system.

Figure 8-2 MicroTCA Redundant Clock Distribution Interface Example