Half-duplex M-LVDS transceiver



Product details


Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • Low-Voltage Differential 30-Ω to 55-Ω Line Drivers
    and Receivers for Signaling Rates(1) up to
    100 Mbps, Clock Frequencies up to 50 MHz
  • Type-1 Receivers Incorporate 25 mV of
    Hysteresis (SN65MLVD200A, SN65MLVD202A)
  • Type-2 Receivers Provide an Offset (100 mV)
    Threshold to Detect Open-Circuit and Idle-Bus
    Conditions (SN65MLVD204A, SN65MLVD205A)
  • Meets or Exceeds the M-LVDS Standard
    TIA/EIA-899 for Multipoint Data Interchange
  • Controlled Driver Output Voltage Transition Times
    for Improved Signal Quality
  • –1 V to 3.4 V of Common-Mode Voltage Range
    Allows Data Transfer With 2 V of Ground Noise
  • Bus Pins High Impedance When Disabled
    or VCC ≤ 1.5 V
  • 200-Mbps Devices Available (SN65MLVD201,
    SN65MLVD203, SN65MLVD206, SN65MLVD207)
  • Bus Pin ESD Protection Exceeds 8 kV
  • Packages Available:
    • 8-Pin SOIC
      SN65MLVD200A, SN65MLVD204A
    • 14-Pin SOIC
      SN65MLVD202A, SN65MLVD205A
  • Improved Alternatives to the SN65MLVD200,
    SN65MLVD202A, SN65MLVD204A, and
    SN65MLVD205A Devices
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The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.

The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.

The devices are characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet (Rev. D) Oct. 28, 2015
Application note How Far, How Fast Can You Operate MLVDS? Aug. 06, 2018
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. B) Apr. 26, 2013
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) Nov. 20, 2001

Design & development

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Hardware development

document-generic User guide
document-generic User guide
This evaluation module is for the SN65MLVD203B and SN65MLVD204B, which are M-LVDS transceivers.
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
  • Can combine MLVD20XBEVM boards to simulate multiple receiver nodes
  • Includes footprints for D package version of devices, so entire family of SN65MLVD20X transceivers can be evaluated
  • Flexible termination
  • This evaluation module has the complete circuit for the full-duplex and half-duplex M-LVDS (...)

Design tools & simulation

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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
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