SNOSDL9B December   2024  – May 2026 LMG5126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Multi-Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSA, CSB)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSA, CSB)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 GAN Drivers, Integrated Boot Capacitor and Diode, and Hiccup Mode Fault Protection
      17. 6.3.17 Signal Deglitch Overview
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  Determine the Total Phase Number
        3. 7.2.3.3  Determining the Duty Cycle
        4. 7.2.3.4  Timing Resistor RT
        5. 7.2.3.5  Inductor Selection Lm
        6. 7.2.3.6  Current Sense Resisitor Rcs
        7. 7.2.3.7  Current Sense Filter RCSFA, RCSFB, CCS
        8. 7.2.3.8  Snubber Components
        9. 7.2.3.9  Vout Programming
        10. 7.2.3.10 Input Current Limit (ILIM/IMON)
        11. 7.2.3.11 Minimum Load Resistor
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 Output Capacitor Cout
        15. 7.2.3.15 Input Capacitor Cin
        16. 7.2.3.16 VCC Capacitor CVCC
        17. 7.2.3.17 BIAS Capacitor
        18. 7.2.3.18 VOUT Capacitor
        19. 7.2.3.19 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3.10 Input Current Limit (ILIM/IMON)

The transient power is high in audio applications. For this application 400W is selected as peak output power. But the average power is typically much lower than the peak power. 240W is selected as average power. With proper ILIM/IMON setting, the average input current is limited to less than 240W while allowing 400W peak for 300ms. When the average current loop is triggered, VOUT drops till the input and output power is balanced.

The per phase input current at average output power and typical input voltage is found as,

Equation 73. Iavg=Pavg_total1×η×Vin_typ=17.5A

22A is selected as the average input current limit.

Equation 74. Ilim=22A

The current out of ILIM/IMON is found as,

Equation 75. IMON_lim=Rcs×Ilim×GIMON+IOFFSET=2mΩ×22A×0.333mA/V+4μA=18.6μA

RILIM is calculated as:

Equation 76. RIMON=VILIMIMON=1V11μA=53.7kΩ

A standard value of 53.6kΩ is chosen for RIMON.

As shown in Figure 7-6, use CIMON and Rc to create a proper delay before the average current loop is triggered.

LMG5126 ILIM/IMON Pin ConfigurationFigure 7-6 ILIM/IMON Pin Configuration

In this application 300ms delay for 400W is required.

At zero load current out of ILIM/IMON is found as,

Equation 77. IMON_0A=IOFFSET=4μA

The ILIM/IMON voltage at zero load is calculated as,

Equation 78. VIMON_0A=RIMON×IMON_0A=0.21V

At 400W, 1.6 times the rated power, the current out of ILIM/IMON is found as,

Equation 79. IMON_tr=Rcs×1.6×Ilim×GIMON+IOFFSET=2mΩ×35.2A×0.333mA/V+4μA=27.4μA

CIMON is determined by,

Equation 80. CIMON=tdelayRIMON×lnRIMON×IMON_tr-VIMON_0ARIMON×IMON_tr-VILIM_th=4.5μF

A standard value of 4.7μF is chosen for CIMON.

Rc is determined by,

Equation 81. Rc=120π×CIMON=3.38k

A standard value of 3.4kΩ is chosen for Rc.