SNOSDL9B December   2024  – May 2026 LMG5126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Multi-Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSA, CSB)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSA, CSB)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 GAN Drivers, Integrated Boot Capacitor and Diode, and Hiccup Mode Fault Protection
      17. 6.3.17 Signal Deglitch Overview
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  Determine the Total Phase Number
        3. 7.2.3.3  Determining the Duty Cycle
        4. 7.2.3.4  Timing Resistor RT
        5. 7.2.3.5  Inductor Selection Lm
        6. 7.2.3.6  Current Sense Resisitor Rcs
        7. 7.2.3.7  Current Sense Filter RCSFA, RCSFB, CCS
        8. 7.2.3.8  Snubber Components
        9. 7.2.3.9  Vout Programming
        10. 7.2.3.10 Input Current Limit (ILIM/IMON)
        11. 7.2.3.11 Minimum Load Resistor
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 Output Capacitor Cout
        15. 7.2.3.15 Input Capacitor Cin
        16. 7.2.3.16 VCC Capacitor CVCC
        17. 7.2.3.17 BIAS Capacitor
        18. 7.2.3.18 VOUT Capacitor
        19. 7.2.3.19 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3.14 Output Capacitor Cout

The output capacitors smooth the output voltage ripple and provide a source of charge during load transient conditions.

Ripple current rating of output capacitor must be carefully selected. In boost regulator, the output is supplied by discontinuous current and the ripple current requirement is usually high. In practice, the ripple current requirement can be dramatically reduced by placing high-quality ceramic capacitors earlier than the bulk aluminum capacitors close to the power switches.

The output voltage ripple is dominated by ESR of the output capacitors. Paralleling output capacitor is a good choice to minimize effective ESR and split the output ripple current into capacitors.

The single phase boost output RMS ripple current can be expressed as:

Equation 86. I 1 p _ r m s ≅ I o u t × D D '

The output RMS current is reduced with interleaving as shown in Figure 7-7. Dual phase interleaved boost output RMS ripple current can be expressed as:

Equation 87. I o u t _ 2 p _ r m s ≅ I o u t 2 × D × 1 - 2 D D ' ,     D < 0.5 I o u t 2 × 2 D - 1 D ' ,     D ≥ 0.5
LMG5126 Normalized Output Capacitor RMS Ripple CurrentFigure 7-7 Normalized Output Capacitor RMS Ripple Current

Decoupling capacitors are critical for minimized voltage spike of the MOSFETs. This is also important from EMI view. Quite a few 0603/100nF ceramic capacitors are placed close to the MOSFETs following "vertical loop" concept. Refer to Improve High-Current DC/DC Regulator EMI Performance for Free With Optimized Power Stage Layout application brief for more details.

A few 10µF ceramic capacitors are also necessary to reduce the output voltage ripple and split the output ripple current.

Typically, aluminum capacitors are required for high capacitance. In this example, four 150µF aluminum capacitors are selected.

The output transient response is closely related to the bandwidth of the loop gain and the output capacitance. According to How to Determine Bandwidth from the Transient-response Measurement technical article, the overshoot or undershoot Vp can be estimated as:

Equation 88. Vp=ΔItran2π×fc×Cout

where ΔItran is the transient load current step.

Please be aware that Equation 88 is valid only if the converter is always operating in CCM or FPWM during load step. If the converter enters DCM or pulsing skip mode at light load, the overshoot is worse.

Due to the inherent path from input to output, unlimited inrush current can flow when the input voltage rises quickly and charges the output capacitor. The slew rate of input voltage rising must be controlled by a hot-swap or by starting the input power supply softly for the inrush current not to damage the inductor, sense resistor or high-side FET.