SNOSDL9B December   2024  – May 2026 LMG5126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Multi-Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSA, CSB)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSA, CSB)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 GAN Drivers, Integrated Boot Capacitor and Diode, and Hiccup Mode Fault Protection
      17. 6.3.17 Signal Deglitch Overview
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  Determine the Total Phase Number
        3. 7.2.3.3  Determining the Duty Cycle
        4. 7.2.3.4  Timing Resistor RT
        5. 7.2.3.5  Inductor Selection Lm
        6. 7.2.3.6  Current Sense Resisitor Rcs
        7. 7.2.3.7  Current Sense Filter RCSFA, RCSFB, CCS
        8. 7.2.3.8  Snubber Components
        9. 7.2.3.9  Vout Programming
        10. 7.2.3.10 Input Current Limit (ILIM/IMON)
        11. 7.2.3.11 Minimum Load Resistor
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 Output Capacitor Cout
        15. 7.2.3.15 Input Capacitor Cin
        16. 7.2.3.16 VCC Capacitor CVCC
        17. 7.2.3.17 BIAS Capacitor
        18. 7.2.3.18 VOUT Capacitor
        19. 7.2.3.19 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

9 Revision History

Changes from Revision A (December 2025) to Revision B (May 2026)

  • Updated exposed die SW and PGND connection in Pin Configuration and Functions Go
  • Deleted Absolute Maximum Ratings table line: SW, VOUT current (pulsed, 300µs), TJ = 25°CGo
  • Changed ESD ratings table from automotive to commercial.Go
  • Updated Figure 6-1 to align the external resistor divider naming with the formula namingGo
  • Added Figure 6-7 Go
  • Added text: For multi-device operation, the primary device sets the operation mode and the secondary devices follow according to Table 6-4 in Operation Modes (BYPASS, DEM, FPWM) Go
  • Updated Figure 6-26 reflecting correct device behaviorGo

Changes from Revision * (December 2024) to Revision A (December 2025)

  • Changed data sheet status from Advance Information to Production DataGo