SNOSDL9B December   2024  – May 2026 LMG5126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Configuration
      2. 6.3.2  Device Enable/Disable (UVLO/EN)
      3. 6.3.3  Multi-Device Operation
      4. 6.3.4  Switching Frequency and Synchronization (SYNCIN)
      5. 6.3.5  Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Operation Modes (BYPASS, DEM, FPWM)
      7. 6.3.7  VCC Regulator, BIAS (BIAS-pin, VCC-pin)
      8. 6.3.8  Soft Start (SS-pin)
      9. 6.3.9  VOUT Programming (VOUT, ATRK, DTRK)
      10. 6.3.10 Protections
        1. 6.3.10.1 VOUT Overvoltage Protection (OVP)
        2. 6.3.10.2 Thermal Shutdown (TSD)
      11. 6.3.11 Power-Good Indicator (PGOOD-pin)
      12. 6.3.12 Slope Compensation (CSA, CSB)
      13. 6.3.13 Current Sense Setting and Switch Peak Current Limit (CSA, CSB)
      14. 6.3.14 Input Current Limit and Monitoring (ILIM, IMON, DLY)
      15. 6.3.15 Maximum Duty Cycle and Minimum Controllable On-time Limits
      16. 6.3.16 GAN Drivers, Integrated Boot Capacitor and Diode, and Hiccup Mode Fault Protection
      17. 6.3.17 Signal Deglitch Overview
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown State
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Feedback Compensation
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1  Custom Design With WEBENCH® Tools
        2. 7.2.3.2  Determine the Total Phase Number
        3. 7.2.3.3  Determining the Duty Cycle
        4. 7.2.3.4  Timing Resistor RT
        5. 7.2.3.5  Inductor Selection Lm
        6. 7.2.3.6  Current Sense Resisitor Rcs
        7. 7.2.3.7  Current Sense Filter RCSFA, RCSFB, CCS
        8. 7.2.3.8  Snubber Components
        9. 7.2.3.9  Vout Programming
        10. 7.2.3.10 Input Current Limit (ILIM/IMON)
        11. 7.2.3.11 Minimum Load Resistor
        12. 7.2.3.12 UVLO Divider
        13. 7.2.3.13 Soft Start
        14. 7.2.3.14 Output Capacitor Cout
        15. 7.2.3.15 Input Capacitor Cin
        16. 7.2.3.16 VCC Capacitor CVCC
        17. 7.2.3.17 BIAS Capacitor
        18. 7.2.3.18 VOUT Capacitor
        19. 7.2.3.19 Loop Compensation
      4. 7.2.4 Application Curves
        1. 7.2.4.1 Efficiency
        2. 7.2.4.2 Steady State Waveforms
        3. 7.2.4.3 Step Load Response
        4. 7.2.4.4 Thermal Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Typical values correspond to TJ = 25 °C. Minimum and maximum limits apply over TJ = -40 °C to 150 °C. Unless otherwise stated, VI = VBIAS = 12 V, VOUT = 24 V, fSW = 400 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (BIAS, VCC)
ISD VI current in shutdown state (BIAS connected to VI). Current into BIAS, CSA, CSB, SW. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 5 100 µA
ISD_BIAS BIAS-pin current in shutdown state. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 2 5 µA
ISD_VOUT VOUT-pin current in shutdown state. VUVLO/EN = 0V, VOUT = 12V, TJ = –40°C to 85°C 0.001 0.5 µA
IQ_BIAS_FPWM BIAS-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching, RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 1.5 2.5 mA
IQ_BIAS_DEM BIAS-pin quiescent current  in active state, DEM-Mode, internal clock (not-switching, RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 1.6 2 mA
IQ_VOUT_FPWM VOUT-pin quiescent current in active state, FPWM-Mode, internal clock (not-switching). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VATRK = 0.8V, no load, TJ = –40°C to 125°C 20 750 µA
IQ_BIAS_BYP BIAS-pin current in bypass state (RT and IMON current is excluded). VUVLO/EN = 2.0V, CFG1 = level 10, CFG2 = level 1, VOUT = 12V, TJ = –40°C to 125°C 1.5 8.5 mA
IBIAS BIAS-pin bias current when VCC is supplied by BIAS,  FPWM-Mode (not-switching, RT and IMON current is excluded). VBIAS = 12V, IVCC = 100mA 100 110 mA
IVOUT VOUT-pin bias current when VCC is supplied by VOUT,  FPWM-Mode (not-switching). VBIAS = 3.3V, IVCC = 100mA 100 110 mA
VCC REGULLATOR (VCC)
VBIAS-RISING Threshold to switch VCC supply from VOUT-pin to BIAS-pin VBIAS rising 6.0 6.25 6.5 V
VBIAS-FALLING Threshold to switch VCC supply from BIAS-pin to VOUT-pin VBIAS falling 5.6 5.9 6.2 V
VBIAS-HYS VCC supply threshold hysteresis 250 350 mV
VVCC-REG1 VCC regulation No load 5.1 5.3 5.5 V
VVCC-REG2 VCC regulation during dropout VBIAS = 5.9V, IVCC = 100mA 4.5 5.2 V
VVCC-UVLO-RISING VCC UVLO threshold VCC rising 4.1 4.2 4.3 V
VVCC-UVLO-FALLING VCC UVLO threshold VCC falling 3.8 3.9 4.0 V
VVCC-UVLO-HYS VCC UVLO threshold hysteresis VCC falling 300 mV
IVCC-CL VCC sourcing current limit VVCC = 4V 100 mA
ENABLE (EN/UVLO)
VEN-RISING Enable threshold EN rising 0.50 0.55 0.6 V
VEN-FALLING Enable threshold EN falling 0.40 0.45 0.50 V
VEN-HYS Enable hysteresis EN falling 75 mV
REN EN pulldown resistance VEN = 0.2V 30 37 50 kΩ
VUVLO-RISING UVLO threshold UVLO rising 1.05 1.1 1.15 V
VUVLO-FALLING UVLO threshold UVLO falling 1.025 1.075 1.125 V
VUVLO-HYS UVLO hysteresis UVLO falling 25 mV
IUVLO-HYS UVLO pulldown hysteresis current VUVLO  = 0.7V 9 10 11 µA
IUVLO/EN UVLO/EN-pin bias current VUVLO/EN = 0.3V, pull-down resistor = active. 8 11 µA
VUVLO/EN = 0.7V, 10µA current = active. 9 10 11 µA
VUVLO/EN = 3.3V 1 µA
POWER SWITCH
RDS(on) GaN FET on resistance High-side TJ = 25°C 4 8.5 mΩ
Low-side 4 8.5 mΩ
CONFIGURATION (CFG1, CFG2, SYNCOUT)
RCFGx_1 CFGx level 1 resistance 0 0.1 kΩ
RCFGx_2 CFGx level 2 resistance 0.496 0.51 0.526 kΩ
RCFGx_3 CFGx level 3 resistance 1.11 1.15 1.19 kΩ
RCFGx_4 CFGx level 4 resistance 1.81 1.9 1.93 kΩ
RCFGx_5 CFGx level 5 resistance 2.65 2.7 2.82 kΩ
RCFGx_6 CFGx level 6 resistance 3.71 3.8 3.94 kΩ
RCFGx_7 CFGx level 7 resistance 4.95 5.1 5.26 kΩ
RCFGx_8 CFGx level 8 resistance 6.29 6.5 6.68 kΩ
RCFGx_9 CFGx level 9 resistance 8.00 8.3 8.50 kΩ
RCFGx_10 CFGx level 10 resistance 10.18 10.5 10.81 kΩ
RCFGx_11 CFGx level 11 resistance 12.90 13.3 13.70 kΩ
RCFGx_12 CFGx level 12 resistance 15.71 16.2 16.69 kΩ
RCFGx_13 CFGx level 13 resistance 19.88 20.5 21.11 kΩ
RCFGx_14 CFGx level 14 resistance 24.15 24.9 25.65 kΩ
RCFGx_15 CFGx level 15 resistance 29.20 30.1 31.00 kΩ
RCFGx_16 CFGx level 16 resistance 35.40 36.5 38.60 kΩ
RSYNCOUT_1 SYNCOUT level 1 resistance 0 24.9 26.15 kΩ
RSYNCOUT_2 SYNCOUT level 2 resistance 29.94 31.5 33.09 kΩ
RSYNCOUT_3 SYNCOUT level 3 resistance 37.92 39.9 41.91 kΩ
RSYNCOUT_4 SYNCOUT level 4 resistance 46.17 48.6 51.03 kΩ
RSYNCOUT_5 SYNCOUT level 5 resistance 58.44 61.5 64.59 kΩ
RSYNCOUT_6 SYNCOUT level 6 resistance 70.98 75 78.45 kΩ
RSYNCOUT_7 SYNCOUT level 7 resistance 85.8 90.9 94.83 kΩ
RSYNCOUT_8 SYNCOUT level 8 resistance 104.04 110 200 kΩ
SWITCHING FREQUENCY
VRT RT regulation 0.7 0.75 0.8 V
fSW1 Switching frequency fSW = 300kHz, RT = 104.4kΩ 255 300 345 kHz
fSW2 fSW = 2500kHz, RT = 12kΩ 2250 2500 2750 kHz
tON-MIN Minimum controllable on-time fSW = 2500kHz 14 20 50 ns
tOFF-MIN Minimum forced off-time fSW = 2500kHz 45 65 85 ns
DMAX1 Maximum duty cycle limit  fSW = 300kHz 97% 98% 99%
DMAX2 fSW = 2500kHz 78% 84% 90%
SYNCHRONIZATION (SYNCIN, SYNCOUT)
fSYNC_DET_min SYNCIN frequency activity detection Spread Spectrum = off fSW = 300kHz 120 kHz
fSYNC_DET SYNCIN frequency activity detection vs RT set switching frequency Spread Spectrum = off RT = 12kΩ to 104.4kΩ –60%
SYNCIN activity detection cycles 3 cycles
fSYNC Syncing frequency range from RT set frequency during synchronization. single device Frequency synchronized to ext. clock min. = 300kHz, max. = 2500kHz. –45% 45%
multi device –22% 22%
VSYNCIN_H SYNCIN high level input voltage SYNCIN rising 1.19 5.25 V
VSYNCIN_L SYNCIN low level input voltage SYNCIN falling –0.3 0.41 V
ISYNCIN SYNCIN bias current 0.01 1 µA
Minimum SYNCIN pullup / pulldown pulse width 135 ns
VOUT PROGRAMMING (ATRK/DTRK)
VOUT_REG VOUT regulation with ATRK voltage ATRK = 0.2V, VI = 4.5V 5.85 6 6.15 V
ATRK = 0.4V, VI = 10V 11.82 12 12.18 V
ATRK = 0.8V 23.64 24 24.36 V
ATRK = 1.6V 47.28 48 48.72 V
ATRK = 2V 59.10 60 60.90 V
GDTRK Conversion ratio of DTRK duty cycle to VATRK fDTRK = 100kHz, 2200kHz 25 mV / %
DTRK duty cycle range 8% 80%
VATRK ATRK voltage for given DTRK duty cycle fDTRK = 100kHz, DC = 8% 0.192 0.2 0.208 V
fDTRK = 100kHz, DC = 40% 0.98 1 1.02 V
fDTRK = 100kHz, DC = 80% 1.98 2 2.02 V
fDTRK = 500kHz, DC = 8% 0.19 0.2 0.215 V
fDTRK = 500kHz, DC = 40% 0.98 1 1.02 V
fDTRK = 500kHz, DC = 80% 1.98 2 2.02 V
VDTRK_H DTRK high level input voltage DTRK rising 1.19 5.25 V
VDTRK_L DTRK low level input voltage DTRK falling –0.3 0.41 V
IATRK Source current when activated through resistor setting at SYNCOUT 19.8 20 20.2 µA
IATRK/DTRK ATRK/DTRK-pin bias current 20µA current is disabled, VATRK/DTRK = 2V 0.01 1 µA
Minimum DTRK pull-up / pull-down pulse width 25 ns
SOFT START (SS)
ISS Soft-start current 42.5 50 57.5 µA
VSS-DONE Soft-start done threshold 2.15 2.2 2.25 V
RSS SS pulldown switch RDSON 37 70 Ω
VSS-DIS SS discharge detection threshold 20 45 70 mV
CURRENT SENSE (CSA, CSB)
ACS Current sense amplifier gain 10 V/V
VCLTH Positive peak current limit threshold 60mV sensing Referenced to CS input 54 60 66 mV
29mV sensing 24 29 35 mV
VNCLTH Negative peak current limit threshold 60mV and 29mV sensing Referenced to CS input, FPWM mode –34 –28 –22 mV
VICL Input current limit 60mV sensing Referenced to CS input 64 72 84 mV
29mV sensing 30 38 45 mV
ΔVICL_CLTH Delta voltage between ICL and positive peak current threshold 60mV sensing Delta voltage between ICL and positive peak current threshold 6 12 mV
29mV sensing 3 6 mV
Peak current limit trip delay 60 ns
VZCD ZCD threshold (CSA – CSB) CS input falling, DEM 0 3 6 mV
CS input falling, DEM, TJ = 0°C to 85°C 0 3 5 mV
VZCD_BYP ZCD threshold in bypass mode (CSA – CSB). –6 –2.5 0 mV
VSLOPE Peak slope compensation amplitude Referenced to CS input, fSW = 300kHz 40 45 52 mV
ICSA CSA current Device in Standby state, VI = VBIAS = VOUT = 12V 150 170 µA
ICSB CSB current 1.2 µA
CURRENT MONITOR / LIMITER WITH DELAY (IMON/ILIM)
GIMON Transconductance Gain 0.320 0.333 0.346 μA/mV
IOFFSET Offset current 2.7 4 5 μA
VILIM ILIM regulation target 0.93 1 1.07 V
VILIM_th ILIM activation threshold 1.05 1.1 1.25 V
VILIM_reset DLY reset threshold ILIM falling, referenced to VILIM 85% 89% 93%
IDLY DLY sourcing/sinking current 4 5 6 μA
VDLY_peak_rise VDLY rising 2.45 2.6 2.75 V
VDLY_peak_fall VDLY falling 2.25 2.4 2.55 V
VDLY_valley 0.2 V
ERROR AMPLIFIER (COMP)
Gm Transconductance 0.7 1 1.3 mA/V
ACOMP-PWM COMP-to-PWM gain 1 V/V
VCOMP-MAX COMP maximum clamp voltage COMP rising 2.3 2.55 2.9 V
VCOMP-MIN COMP minimum clamp voltage, active in DEM COMP falling 0.38 0.48 0.55 V
COMP minimum clamp voltage, active in FPWM COMP falling 0.13 0.16 0.19 V
VCOMP-offset Offset in respect to min clamp COMP falling 0.01 0.03 0.06 V
ISOURCE-MAX Maximum COMP sourcing current VCOMP = 1V, VATRK = 2V 150 µA
ISINK-MAX Maximum COMP sinking current VCOMP = 1V, VATRK = 0.5V 90 µA
OPERATION MODES
VMODE_H MODE-pin high level FPWM 1.19 5.25 V
VMODE_L MODE-pin low level DEM –0.3 0.41 V
IMODE MODE-pin bias current MODE = 3.3V 0.01 1 µA
OVERVOLTAGE AND UNDERVOLTAGE MONITOR
VOVP-H Overvoltage threshold rising VOUT rising (referenced to error amplifier reference) 108% 110% 112%
VOVP-L Overvoltage threshold falling VOUT falling (referenced to error amplifier reference) 101% 103% 105%
VOVP_max-H Max. overvoltage threshold rising 25V setting VOUT rising (referenced to error amplifier reference) 23 24 25 V
35V setting 33 34 35 V
50V setting 48 49 50 V
65V setting 63 64 65 V
VOVP_max-L Max. overvoltage threshold falling 25V setting VOUT falling (referenced to error amplifier reference) 22 23 24 V
35V setting 32 33 34 V
50V setting 47 48 49 V
65V setting 62 63 64 V
VUVP-H Undervoltage threshold VOUT rising (referenced to error amplifier reference) 91% 93% 95%
VUVP-L Undervoltage threshold VOUT falling (referenced to error amplifier reference) 88% 90% 92%
PGOOD
RPGOOD PGOOD pull-down switch RDSON 1mA sinking 90 180 Ω
Minimum BIAS for valid PGOOD R5V = 7.81kΩ, VPGOOD < 0.4V 2 V
THERMAL SHUTDOWN (TSD)
TTSD-RISING Thermal shutdown threshold Temperature rising 175 °C
TTSD-HYS Thermal shutdown hysteresis 15 °C
TIMINGS
td Dead time Driver setting = strong 5 ns
STANDBYtimer STANDBY timer 130 150 170 µs