SNOSDL9 Data sheet

SNOSDL9B December 2024 – May 2026 LMG5126

PRODUCTION DATA

7.2.3.9 V_out Programming

For fixed output voltage, V_OUT can be programmed by connecting a resistor to ATRK/DTRK and turn on precise internal 20μA current source.

Equation 59.

R_{A T R K} = \frac{V_{o u t_m a x}}{6 V} \times 10 k Ω = 75 k Ω

For class-H audio application, V_out can be adjusted to optimize the efficiency. Analog tracking or digital tracking can be applied with ATRK/DTRK.

For analog tracking, apply a voltage to ATRK/DTRK to program V_out. The voltage can be found as:

Equation 60.

V_{A T R K_m a x} = \frac{V_{o u t_m a x}}{30} = 1.5 V

Equation 61.

V_{A T R K_n o m} = \frac{V_{o u t_nom}}{30} = 0.8 V

The output voltage can also be programmed by digital PWM signal (DTRK). The duty cycle D_TRK can be found as:

Equation 62.

D_{T R K} = \frac{V_{o u t_m a x}}{0.75 V} \times 100 % = 60 %

Equation 63.

D_{T R K_m i n} = \frac{V_{o u t_m i n}}{0.75 V} \times 100 % = 10.7 %

Make sure the DTRK frequency is between 100kHz and 2200kHz. The DTRK PWM signal must be applied when the IC is enabled.

A two stage RC filter with offset can be utilized to convert a digital PWM signal to analog voltage as shown in Figure 7-5.

LMG5126 Two Stage RC Filter to ATRK/DTRK

Figure 7-5 Two Stage RC Filter to ATRK/DTRK

The two stage RC filter is used to filter the PWM signal into a smooth analog voltage. The two stage RC filter is selected considering voltage ripple and settling time on ATRK/DTRK.

100% PWM duty cycle sets the output voltage to V_{out_max} and 0% PWM duty cycle sets the output voltage to V_{out_min}. R_t and R_b are used to adjust ATRK/DTRK offset voltage.

The V_{trk_max} and V_{trk_min} can be found as,

Equation 64.

V_{A T R K_m a x} = V_{d d} \frac{R_{b}}{({2 R}_{f} + R_{a}) ‖R_{t} + R_{b}}

Equation 65.

V_{A T R K_m i n} = V_{d d} \frac{({2 R}_{f} + R_{a}) ‖R_{b}}{({2 R}_{f} + R_{a}) ‖R_{b} + R_{t}}

Where V_dd is the amplitude of the PWM signal; d is the PWM duty cycle.

The AC transfer function from input to V_ATRK can be found as,

Equation 66.

G_{t r k} (s) = \frac{\frac{R_{L}}{2 R_{f} + R_{L}}}{1 + 2 ζ \frac{s}{ω_{n}} + {(\frac{s}{ω_{n}})}^{2}}

Where

Equation 67.

R_{L} = R_{a} + R_{b} ‖R_{t}

Equation 68.

ω_{n} = \frac{1}{R_{f} \times C_{f} \sqrt{\frac{R_{L}}{2 R_{f} + R_{L}}}}

Equation 69.

ζ = \frac{1}{2} (\frac{R_{f}}{R_{L}} + 3) \sqrt{\frac{R_{L}}{2 R_{f} + R_{L}}}

The roots of the denominator can be found as,

Equation 70.

s_{1} = - ζ ω_{n} + ω_{n} \sqrt{ζ^{2} - 1}

Equation 71.

s_{2} = - ζ ω_{n} - ω_{n} \sqrt{ζ^{2} - 1}

As ζ>1, this is an over-damped second order system. s₁ is the dominate pole. 2% settling time t_s can be estimated as,

Equation 72.

t_{s} = \frac{1}{s_{1}} \times l n (- \frac{0.02 \times 2 s_{1} \sqrt{ζ^{2} - 1}}{ω_{n}})

In this application, 400kHz PWM frequency is used. R_f=4.99kΩ, C_f=47nF, R_a=1.5kΩ, R_t=51kΩ, R_b=7.87kΩ are selected. The 2% settling time is around 1.3ms.

7.2.3.9 Vout Programming

7.2.3.9 V_out Programming