SPRADL9 February 2025 CC1310
As mentioned previously, the 12bit, analog-to-digital converter (ADC) peripheral block included in CC13x2 and CC26x2 devices, which is typically used by the Sensor Controller, requires the SCLK_HF signal, and is therefore not available in low-power (2MHz) mode. The goal of this section is to highlight an alternative design creating an 8bit, successive-approximation (SAR)-type, low-power, ADC using the CC13x2/4 and CC26x2/4 Sensor Controller running in 2MHz mode. In this design, the comparator and digital-to-analog converter (DAC) peripherals are used which are available in low-power mode.
Figure 3-12 SAR ADC Block DiagramThe SAR ADC consists of four major blocks: