SPRSP69D July   2023  – August 2025 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      3. 5.5.3 USB Pin Muxing
      4. 5.5.4 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.12.3.4.7.2 Crystal Oscillator Parameters
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC INL and DNL
          10. 6.13.2.2.10 ADC Performance Per Pin
          11. 6.13.2.2.11 ADC Input Models
          12. 6.13.2.2.12 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
            1. 6.14.7.1.1.1 SDFM Timing Requirements When Using Synchronized GPIO - SYNC Option
          2. 6.14.7.1.2 SDFM Electrical Data and Timing (Using ASYNC)
            1. 6.14.7.1.2.1 SDFM Timing Requirements When Using Async GPIO and SDFM Sync to PLL
          3. 6.14.7.1.3 SDFM Timing Diagram
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.3.1 Analog Signals

Table 5-2 Analog Signals
SIGNAL NAME PIN TYPE DESCRIPTION 256 ZEJ 176 PTP 169 NMR 100 PZP
A0 I ADC-A Input 0 P1 43 L3 25
A1 I ADC-A Input 1 P2 42 K3 24
A2 I ADC-A Input 2 N3 41 J3 23
A3 I ADC-A Input 3 N4 40 H3 22
A4 I ADC-A Input 4 M4 39 H2 21
A5 I ADC-A Input 5 M5 38 H1 20
A6 I ADC-A Input 6 N6 57 J5 38
A7 I ADC-A Input 7 P6 58 K5
A8 I ADC-A Input 8 R6 59 J6
A9 I ADC-A Input 9 T7 60 K6
A10 I ADC-A Input 10 T8 62 L5 39
A11 I ADC-A Input 11 R8 63 L6 40
A12 I ADC-A Input 12 P1 43 L3 25
A14 I ADC-A Input 14 R1 44 M1 26
A15 I ADC-A Input 15 R2 45 M2 27
AIO225 I Analog Pin Used For Digital Input 225 R1 44 M1 26
AIO226 I Analog Pin Used For Digital Input 226 R2 45 M2 27
AIO227 I Analog Pin Used For Digital Input 227 P1 43 L3 25
AIO228 I Analog Pin Used For Digital Input 228 P2 42 K3 24
AIO229 I Analog Pin Used For Digital Input 229 N3 41 J3 23
AIO230 I Analog Pin Used For Digital Input 230 N4 40 H3 22
AIO231 I Analog Pin Used For Digital Input 231 M4 39 H2 21
AIO232 I Analog Pin Used For Digital Input 232 M5 38 H1 20
AIO233 I Analog Pin Used For Digital Input 233 T2 46 N2 28
AIO234 I Analog Pin Used For Digital Input 234 T3 47 N3 29
AIO235 I Analog Pin Used For Digital Input 235 R3 48 M3 30
AIO236 I Analog Pin Used For Digital Input 236 P3 49 L4 31
AIO237 I Analog Pin Used For Digital Input 237 L4 31 H4 15
AIO238 I Analog Pin Used For Digital Input 238 R5
AIO239 I Analog Pin Used For Digital Input 239 K1
AIO240 I Analog Pin Used For Digital Input 240 P4 51
AIO241 I Analog Pin Used For Digital Input 241 L3
AIO242 I Analog Pin Used For Digital Input 242 K2
B0 I ADC-B Input 0 T2 46 N2 28
B1 I ADC-B Input 1 T3 47 N3 29
B2 I ADC-B Input 2 R3 48 M3 30
B3 I ADC-B Input 3 P3 49 L4 31
B4 I ADC-B Input 4 P7 64 M6
B5 I ADC-B Input 5 N7 65 N6
B6 I ADC-B Input 6 N5 55 J4 36
B7 I ADC-B Input 7 P5 56 K4 37
B8 I ADC-B Input 8 P8 66 M7
B9 I ADC-B Input 9 N8 67 N7
B10 I ADC-B Input 10 R7 61
B11 I ADC-B Input 11 P4 51
B12 I ADC-B Input 12 P1 43 L3 25
B13 I ADC-B Input 13 R5
B14 I ADC-B Input 14 R1 44 M1 26
B15 I ADC-B Input 15 R2 45 M2 27
B19 I ADC-B Input 19 P2 42 K3 24
B20 I ADC-B Input 20 N3 41 J3 23
C0 I ADC-C Input 0 H1 22 F1 9
C1 I ADC-C Input 1 J1 23 G1 10
C2 I ADC-C Input 2 L4 31 H4 15
C3 I ADC-C Input 3 L5 30 H5 14
C4 I ADC-C Input 4 M6 29 H6 13
C5 I ADC-C Input 5 L6 28 G6 12
C6 I ADC-C Input 6 K5 27 G5 11
C7 I ADC-C Input 7 K4 26 G4
C8 I ADC-C Input 8 K3 25 G3
C9 I ADC-C Input 9 J2 24 G2
C10 I ADC-C Input 10 L3
C11 I ADC-C Input 11 K2
C12 I ADC-C Input 12 P1 43 L3 25
C13 I ADC-C Input 13 K1
C14 I ADC-C Input 14 R1 44 M1 26
C15 I ADC-C Input 15 R2 45 M2 27
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 N4 40 H3 22
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 P2 42 K3 24
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 N3 41 J3 23
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 P1 43 L3 25
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 P2 42 K3 24
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 N4 40 H3 22
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 N4 40 H3 22
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 P2 42 K3 24
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 N3 41 J3 23
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 P1 43 L3 25
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 P2 42 K3 24
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 P3 49 L4 31
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 M5 38 H1 20
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 N3 41 J3 23
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 M4 39 H2 21
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 P8 66 M7
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 N8 67 N7
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 M5 38 H1 20
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 M5 38 H1 20
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 N3 41 J3 23
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 M4 39 H2 21
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 P8 66 M7
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 N8 67 N7
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 L6 28 G6 12
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 P3 49 L4 31
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 P5 56 K4 37
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 R3 48 M3 30
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 T2 46 N2 28
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 T3 47 N3 29
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 P3 49 L4 31
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 P5 56 K4 37
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0 R3 48 M3 30
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1 T2 46 N2 28
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 T3 47 N3 29
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 L5 30 H5 14
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 R2 45 M2 27
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 R7 61
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0 R1 44 M1 26
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 R7 61
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 P4 51
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 R2 45 M2 27
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 R2 45 M2 27
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 R7 61
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0 R1 44 M1 26
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 R7 61
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2 P4 51
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 P6 58 K5
CMP5_HN0 I CMPSS-5 High Comparator Negative Input 0 L6 28 G6 12
CMP5_HN1 I CMPSS-5 High Comparator Negative Input 1 P7 64 M6
CMP5_HP0 I CMPSS-5 High Comparator Positive Input 0 M6 29 H6 13
CMP5_HP1 I CMPSS-5 High Comparator Positive Input 1 P7 64 M6
CMP5_HP2 I CMPSS-5 High Comparator Positive Input 2 N7 65 N6
CMP5_LN0 I CMPSS-5 Low Comparator Negative Input 0 L6 28 G6 12
CMP5_LN1 I CMPSS-5 Low Comparator Negative Input 1 P7 64 M6
CMP5_LP0 I CMPSS-5 Low Comparator Positive Input 0 M6 29 H6 13
CMP5_LP1 I CMPSS-5 Low Comparator Positive Input 1 P7 64 M6
CMP5_LP2 I CMPSS-5 Low Comparator Positive Input 2 N7 65 N6
CMP5_LP3 I CMPSS-5 Low Comparator Positive Input 3 T7 60 K6
CMP6_HN0 I CMPSS-6 High Comparator Negative Input 0 L5 30 H5 14
CMP6_HN1 I CMPSS-6 High Comparator Negative Input 1 H1 22 F1 9
CMP6_HP0 I CMPSS-6 High Comparator Positive Input 0 L4 31 H4 15
CMP6_HP1 I CMPSS-6 High Comparator Positive Input 1 H1 22 F1 9
CMP6_HP2 I CMPSS-6 High Comparator Positive Input 2 J1 23 G1 10
CMP6_LN0 I CMPSS-6 Low Comparator Negative Input 0 L5 30 H5 14
CMP6_LN1 I CMPSS-6 Low Comparator Negative Input 1 H1 22 F1 9
CMP6_LP0 I CMPSS-6 Low Comparator Positive Input 0 L4 31 H4 15
CMP6_LP1 I CMPSS-6 Low Comparator Positive Input 1 H1 22 F1 9
CMP6_LP2 I CMPSS-6 Low Comparator Positive Input 2 J1 23 G1 10
CMP7_HN0 I CMPSS-7 High Comparator Negative Input 0 P6 58 K5
CMP7_HN1 I CMPSS-7 High Comparator Negative Input 1 N5 55 J4 36
CMP7_HP0 I CMPSS-7 High Comparator Positive Input 0 N6 57 J5 38
CMP7_HP1 I CMPSS-7 High Comparator Positive Input 1 N5 55 J4 36
CMP7_HP2 I CMPSS-7 High Comparator Positive Input 2 P5 56 K4 37
CMP7_LN0 I CMPSS-7 Low Comparator Negative Input 0 P6 58 K5
CMP7_LN1 I CMPSS-7 Low Comparator Negative Input 1 N5 55 J4 36
CMP7_LP0 I CMPSS-7 Low Comparator Positive Input 0 N6 57 J5 38
CMP7_LP1 I CMPSS-7 Low Comparator Positive Input 1 N5 55 J4 36
CMP7_LP2 I CMPSS-7 Low Comparator Positive Input 2 P5 56 K4 37
CMP8_HN0 I CMPSS-8 High Comparator Negative Input 0 T7 60 K6
CMP8_HN1 I CMPSS-8 High Comparator Negative Input 1 T8 62 L5 39
CMP8_HP0 I CMPSS-8 High Comparator Positive Input 0 R6 59 J6
CMP8_HP1 I CMPSS-8 High Comparator Positive Input 1 T8 62 L5 39
CMP8_HP2 I CMPSS-8 High Comparator Positive Input 2 R8 63 L6 40
CMP8_LN0 I CMPSS-8 Low Comparator Negative Input 0 T7 60 K6
CMP8_LN1 I CMPSS-8 Low Comparator Negative Input 1 T8 62 L5 39
CMP8_LP0 I CMPSS-8 Low Comparator Positive Input 0 R6 59 J6
CMP8_LP1 I CMPSS-8 Low Comparator Positive Input 1 T8 62 L5 39
CMP8_LP2 I CMPSS-8 Low Comparator Positive Input 2 R8 63 L6 40
CMP9_HN0 I CMPSS-9 High Comparator Negative Input 0 P1 43 L3 25
CMP9_HN1 I CMPSS-9 High Comparator Negative Input 1 N8 67 N7
CMP9_HP0 I CMPSS-9 High Comparator Positive Input 0 R5
CMP9_HP1 I CMPSS-9 High Comparator Positive Input 1 K1
CMP9_HP2 I CMPSS-9 High Comparator Positive Input 2 P6 58 K5
CMP9_LN0 I CMPSS-9 Low Comparator Negative Input 0 P1 43 L3 25
CMP9_LN1 I CMPSS-9 Low Comparator Negative Input 1 N8 67 N7
CMP9_LP0 I CMPSS-9 Low Comparator Positive Input 0 R5
CMP9_LP1 I CMPSS-9 Low Comparator Positive Input 1 K1
CMP9_LP2 I CMPSS-9 Low Comparator Positive Input 2 M5 38 H1 20
CMP10_HN0 I CMPSS-10 High Comparator Negative Input 0 P8 66 M7
CMP10_HN1 I CMPSS-10 High Comparator Negative Input 1 M6 29 H6 13
CMP10_HP0 I CMPSS-10 High Comparator Positive Input 0 L3
CMP10_HP1 I CMPSS-10 High Comparator Positive Input 1 K5 27 G5 11
CMP10_HP2 I CMPSS-10 High Comparator Positive Input 2 K3 25 G3
CMP10_LN0 I CMPSS-10 Low Comparator Negative Input 0 P8 66 M7
CMP10_LN1 I CMPSS-10 Low Comparator Negative Input 1 M6 29 H6 13
CMP10_LP0 I CMPSS-10 Low Comparator Positive Input 0 L3
CMP10_LP1 I CMPSS-10 Low Comparator Positive Input 1 K5 27 G5 11
CMP10_LP2 I CMPSS-10 Low Comparator Positive Input 2 K3 25 G3
CMP11_HN0 I CMPSS-11 High Comparator Negative Input 0 T2 46 N2 28
CMP11_HN1 I CMPSS-11 High Comparator Negative Input 1 K1
CMP11_HP0 I CMPSS-11 High Comparator Positive Input 0 K2
CMP11_HP1 I CMPSS-11 High Comparator Positive Input 1 K4 26 G4
CMP11_HP2 I CMPSS-11 High Comparator Positive Input 2 J2 24 G2
CMP11_LN0 I CMPSS-11 Low Comparator Negative Input 0 T2 46 N2 28
CMP11_LN1 I CMPSS-11 Low Comparator Negative Input 1 K1
CMP11_LP0 I CMPSS-11 Low Comparator Positive Input 0 K2
CMP11_LP1 I CMPSS-11 Low Comparator Positive Input 1 K4 26 G4
CMP11_LP2 I CMPSS-11 Low Comparator Positive Input 2 J2 24 G2
DACA_OUT O Buffered DAC-A Output. P1 43 L3 25
DACC_OUT O Buffered DAC-C Output. T3 47 N3 29
VDAC I Optional external reference voltage for on-chip DACs. T2 46 N2 28
VREFHIA I ADC-A high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. NOTE: Do not load this pin externally M2 37 K2 19
VREFHIB I ADC-B high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. NOTE: Do not load this pin externally R4 53 M4 34
VREFHIC I ADC-C high reference. This voltage must be driven into the pin from external circuitry. Place at least a 2.2-µF capacitor on this pin for the 12-bit mode, or at least a 22-µF capacitor for the 16-bit mode. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. NOTE: Do not load this pin externally L2 35 J2 19
VREFLOA I ADC-A Low Reference M1 33 K1 16
VREFLOB I ADC-B Low Reference T4 50 N4 32
VREFLOC I ADC-C Low Reference L1 32 J1 16