SPRSP69D July   2023  – August 2025 TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      3. 5.5.3 USB Pin Muxing
      4. 5.5.4 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.12.3.4.7.2 Crystal Oscillator Parameters
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC INL and DNL
          10. 6.13.2.2.10 ADC Performance Per Pin
          11. 6.13.2.2.11 ADC Input Models
          12. 6.13.2.2.12 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Electrical Data and Timing (Synchronized GPIO)
            1. 6.14.7.1.1.1 SDFM Timing Requirements When Using Synchronized GPIO - SYNC Option
          2. 6.14.7.1.2 SDFM Electrical Data and Timing (Using ASYNC)
            1. 6.14.7.1.2.1 SDFM Timing Requirements When Using Async GPIO and SDFM Sync to PLL
          3. 6.14.7.1.3 SDFM Timing Diagram
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.3.1 Addresses of Flash Sectors

Table 7-3 Flash Memory Map
PART NUMBER SECTOR ADDRESS ECC ADDRESS
SIZE START END SIZE START END
ALL TI OTP Bank 0 (for TI use) 1536 x 16 0x0007 2000 0x0007 25FF 128 x 16 0x0107 0400 0x0107 04BF
TI OTP Bank 1 (for TI use) 1536 x 16 0x0007 3000 0x0007 35FF 128 x 16 0x0107 0600 0x0107 06BF
TI OTP Bank 2 (for TI use) 1536 x 16 0x0007 4000 0x0007 45FF 128 x 16 0x0107 0800 0x0107 08BF
TI OTP Bank 3 (for TI use) 1536 x 16 0x0007 5000 0x0007 55FF 128 x 16 0x0107 0A00 0x0107 0ABF
TI OTP Bank 4 (for TI use) 1536 x 16 0x0007 6000 0x0007 65FF 128 x 16 0x0107 0C00 0x0107 0CBF
User Bank 0 (DCSM OTP) 1K x 16 0x0007 8000 0x0007 83FF 128 x 16 0x0107 1000 0x0107 107F
User OTP Bank 1 1K x 16 0x0007 8800 0x0007 8BFF 128 x 16 0x0107 1080 0x0107 10FF
User OTP Bank 2 1K x 16 0x0007 9000 0x0007 93FF 128 x 16 0x0107 1100 0x0107 117F
User OTP Bank 3 1K x 16 0x0007 9800 0x0007 9BFF 128 x 16 0x0107 1180 0x0107 11FF
User OTP Bank 4 1K x 16 0x0007 A000 0x0007 A3FF 128 x 16 0x0107 1200 0x0107 127F
ALL Bank 0(1)
Sector 0 to 127 128K x 16 0x0008 0000 0x0009 FFFF 16K x 16 0x0108 0000 0x0108 3FFF
Bank 1(1)
Sector 0 to 127 128K x 16 0x000A 0000 0x000B FFFF 16K x 16 0x0108 4000 0x0108 7FFF
F28P65xDKx,F28P65xSKx,F28P65xSHx Bank 2(1)
Sector 0 to 127 128K x 16 0x000C 0000 0x000D FFFF 16K x 16 0x0108 8000 0x0108 BFFF
F28P65xDKx,F28P65xSKx Bank 3(1)
Sector 0 to 127 128K x 16 0x000E 0000 0x000F FFFF 16K x 16 0x0108 C000 0x0108 FFFF
F28P65xDKx,F28P65xSKx,F28P65xDHx Bank 4(1)
Sector 0 to 127 128K x 16 0x0010 0000 0x0011 FFFF 16K x 16 0x0109 0000 0x0109 3FFF
(1) Refer to the Flash Sector Offsets table for sector details.
Table 7-4 Flash Sector Offsets
SECTOR OFFSET FROM FLASH BANK START ADDRESS OFFSET FROM FLASH BANK ECC START ADDRESS
SIZE OFFSET SIZE OFFSET
Sector 0 1K x 16 0x0000 0000 128 x 16 0x0000 0000
Sector 1 1K x 16 0x0000 0400 128 x 16 0x0000 0080
Sector 2 1K x 16 0x0000 0800 128 x 16 0x0000 0100
Sector 3 1K x 16 0x0000 0C00 128 x 16 0x0000 0180
Sector 4 1K x 16 0x0000 1000 128 x 16 0x0000 0200
Sector 5 1K x 16 0x0000 1400 128 x 16 0x0000 0280
Sector 6 1K x 16 0x0000 1800 128 x 16 0x0000 0300
Sector 7 1K x 16 0x0000 1C00 128 x 16 0x0000 0380
Sector 8 1K x 16 0x0000 2000 128 x 16 0x0000 0400
Sector 9 1K x 16 0x0000 2400 128 x 16 0x0000 0480
Sector 10 1K x 16 0x0000 2800 128 x 16 0x0000 0500
Sector 11 1K x 16 0x0000 2C00 128 x 16 0x0000 0580
Sector 12 1K x 16 0x0000 3000 128 x 16 0x0000 0600
Sector 13 1K x 16 0x0000 3400 128 x 16 0x0000 0680
Sector 14 1K x 16 0x0000 3800 128 x 16 0x0000 0700
Sector 15 1K x 16 0x0000 3C00 128 x 16 0x0000 0780
Sector 16 1K x 16 0x0000 4000 128 x 16 0x0000 0800
Sector 17 1K x 16 0x0000 4400 128 x 16 0x0000 0880
Sector 18 1K x 16 0x0000 4800 128 x 16 0x0000 0900
Sector 19 1K x 16 0x0000 4C00 128 x 16 0x0000 0980
Sector 20 1K x 16 0x0000 5000 128 x 16 0x0000 0A00
Sector 21 1K x 16 0x0000 5400 128 x 16 0x0000 0A80
Sector 22 1K x 16 0x0000 5800 128 x 16 0x0000 0B00
Sector 23 1K x 16 0x0000 5C00 128 x 16 0x0000 0B80
Sector 24 1K x 16 0x0000 6000 128 x 16 0x0000 0C00
Sector 25 1K x 16 0x0000 6400 128 x 16 0x0000 0C80
Sector 26 1K x 16 0x0000 6800 128 x 16 0x0000 0D00
Sector 27 1K x 16 0x0000 6C00 128 x 16 0x0000 0D80
Sector 28 1K x 16 0x0000 7000 128 x 16 0x0000 0E00
Sector 29 1K x 16 0x0000 7400 128 x 16 0x0000 0E80
Sector 30 1K x 16 0x0000 7800 128 x 16 0x0000 0F00
Sector 31 1K x 16 0x0000 7C00 128 x 16 0x0000 0F80
Sector 32 1K x 16 0x0000 8000 128 x 16 0x0000 1000
Sector 33 1K x 16 0x0000 8400 128 x 16 0x0000 1080
Sector 34 1K x 16 0x0000 8800 128 x 16 0x0000 1100
Sector 35 1K x 16 0x0000 8C00 128 x 16 0x0000 1180
Sector 36 1K x 16 0x0000 9000 128 x 16 0x0000 1200
Sector 37 1K x 16 0x0000 9400 128 x 16 0x0000 1280
Sector 38 1K x 16 0x0000 9800 128 x 16 0x0000 1300
Sector 39 1K x 16 0x0000 9C00 128 x 16 0x0000 1380
Sector 40 1K x 16 0x0000 A000 128 x 16 0x0000 1400
Sector 41 1K x 16 0x0000 A400 128 x 16 0x0000 1480
Sector 42 1K x 16 0x0000 A800 128 x 16 0x0000 1500
Sector 43 1K x 16 0x0000 AC00 128 x 16 0x0000 1580
Sector 44 1K x 16 0x0000 B000 128 x 16 0x0000 1600
Sector 45 1K x 16 0x0000 B400 128 x 16 0x0000 1680
Sector 46 1K x 16 0x0000 B800 128 x 16 0x0000 1700
Sector 47 1K x 16 0x0000 BC00 128 x 16 0x0000 1780
Sector 48 1K x 16 0x0000 C000 128 x 16 0x0000 1800
Sector 49 1K x 16 0x0000 C400 128 x 16 0x0000 1880
Sector 50 1K x 16 0x0000 C800 128 x 16 0x0000 1900
Sector 51 1K x 16 0x0000 CC00 128 x 16 0x0000 1980
Sector 52 1K x 16 0x0000 D000 128 x 16 0x0000 1A00
Sector 53 1K x 16 0x0000 D400 128 x 16 0x0000 1A80
Sector 54 1K x 16 0x0000 D800 128 x 16 0x0000 1B00
Sector 55 1K x 16 0x0000 DC00 128 x 16 0x0000 1B80
Sector 56 1K x 16 0x0000 E000 128 x 16 0x0000 1C00
Sector 57 1K x 16 0x0000 E400 128 x 16 0x0000 1C80
Sector 58 1K x 16 0x0000 E800 128 x 16 0x0000 1D00
Sector 59 1K x 16 0x0000 EC00 128 x 16 0x0000 1D80
Sector 60 1K x 16 0x0000 F000 128 x 16 0x0000 1E00
Sector 61 1K x 16 0x0000 F400 128 x 16 0x0000 1E80
Sector 62 1K x 16 0x0000 F800 128 x 16 0x0000 1F00
Sector 63 1K x 16 0x0000 FC00 128 x 16 0x0000 1F80
Sector 64 1K x 16 0x0001 0000 128 x 16 0x0000 2000
Sector 65 1K x 16 0x0001 0400 128 x 16 0x0000 2080
Sector 66 1K x 16 0x0001 0800 128 x 16 0x0000 2100
Sector 67 1K x 16 0x0001 0C00 128 x 16 0x0000 2180
Sector 68 1K x 16 0x0001 1000 128 x 16 0x0000 2200
Sector 69 1K x 16 0x0001 1400 128 x 16 0x0000 2280
Sector 70 1K x 16 0x0001 1800 128 x 16 0x0000 2300
Sector 71 1K x 16 0x0001 1C00 128 x 16 0x0000 2380
Sector 72 1K x 16 0x0001 2000 128 x 16 0x0000 2400
Sector 73 1K x 16 0x0001 2400 128 x 16 0x0000 2480
Sector 74 1K x 16 0x0001 2800 128 x 16 0x0000 2500
Sector 75 1K x 16 0x0001 2C00 128 x 16 0x0000 2580
Sector 76 1K x 16 0x0001 3000 128 x 16 0x0000 2600
Sector 77 1K x 16 0x0001 3400 128 x 16 0x0000 2680
Sector 78 1K x 16 0x0001 3800 128 x 16 0x0000 2700
Sector 79 1K x 16 0x0001 3C00 128 x 16 0x0000 2780
Sector 80 1K x 16 0x0001 4000 128 x 16 0x0000 2800
Sector 81 1K x 16 0x0001 4400 128 x 16 0x0000 2880
Sector 82 1K x 16 0x0001 4800 128 x 16 0x0000 2900
Sector 83 1K x 16 0x0001 4C00 128 x 16 0x0000 2980
Sector 84 1K x 16 0x0001 5000 128 x 16 0x0000 2A00
Sector 85 1K x 16 0x0001 5400 128 x 16 0x0000 2A80
Sector 86 1K x 16 0x0001 5800 128 x 16 0x0000 2B00
Sector 87 1K x 16 0x0001 5C00 128 x 16 0x0000 2B80
Sector 88 1K x 16 0x0001 6000 128 x 16 0x0000 2C00
Sector 89 1K x 16 0x0001 6400 128 x 16 0x0000 2C80
Sector 90 1K x 16 0x0001 6800 128 x 16 0x0000 2D00
Sector 91 1K x 16 0x0001 6C00 128 x 16 0x0000 2D80
Sector 92 1K x 16 0x0001 7000 128 x 16 0x0000 2E00
Sector 93 1K x 16 0x0001 7400 128 x 16 0x0000 2E80
Sector 94 1K x 16 0x0001 7800 128 x 16 0x0000 2F00
Sector 95 1K x 16 0x0001 7C00 128 x 16 0x0000 2F80
Sector 96 1K x 16 0x0001 8000 128 x 16 0x0000 3000
Sector 97 1K x 16 0x0001 8400 128 x 16 0x0000 3080
Sector 98 1K x 16 0x0001 8800 128 x 16 0x0000 3100
Sector 99 1K x 16 0x0001 8C00 128 x 16 0x0000 3180
Sector 100 1K x 16 0x0001 9000 128 x 16 0x0000 3200
Sector 101 1K x 16 0x0001 9400 128 x 16 0x0000 3280
Sector 102 1K x 16 0x0001 9800 128 x 16 0x0000 3300
Sector 103 1K x 16 0x0001 9C00 128 x 16 0x0000 3380
Sector 104 1K x 16 0x0001 A000 128 x 16 0x0000 3400
Sector 105 1K x 16 0x0001 A400 128 x 16 0x0000 3480
Sector 106 1K x 16 0x0001 A800 128 x 16 0x0000 3500
Sector 107 1K x 16 0x0001 AC00 128 x 16 0x0000 3580
Sector 108 1K x 16 0x0001 B000 128 x 16 0x0000 3600
Sector 109 1K x 16 0x0001 B400 128 x 16 0x0000 3680
Sector 110 1K x 16 0x0001 B800 128 x 16 0x0000 3700
Sector 111 1K x 16 0x0001 BC00 128 x 16 0x0000 3780
Sector 112 1K x 16 0x0001 C000 128 x 16 0x0000 3800
Sector 113 1K x 16 0x0001 C400 128 x 16 0x0000 3880
Sector 114 1K x 16 0x0001 C800 128 x 16 0x0000 3900
Sector 115 1K x 16 0x0001 CC00 128 x 16 0x0000 3980
Sector 116 1K x 16 0x0001 D000 128 x 16 0x0000 3A00
Sector 117 1K x 16 0x0001 D400 128 x 16 0x0000 3A80
Sector 118 1K x 16 0x0001 D800 128 x 16 0x0000 3B00
Sector 119 1K x 16 0x0001 DC00 128 x 16 0x0000 3B80
Sector 120 1K x 16 0x0001 E000 128 x 16 0x0000 3C00
Sector 121 1K x 16 0x0001 E400 128 x 16 0x0000 3C80
Sector 122 1K x 16 0x0001 E800 128 x 16 0x0000 3D00
Sector 123 1K x 16 0x0001 EC00 128 x 16 0x0000 3D80
Sector 124 1K x 16 0x0001 F000 128 x 16 0x0000 3E00
Sector 125 1K x 16 0x0001 F400 128 x 16 0x0000 3E80
Sector 126 1K x 16 0x0001 F800 128 x 16 0x0000 3F00
Sector 127 1K x 16 0x0001 FC00 128 x 16 0x0000 3F80