6.12.5.17.1.5 HS400 Mode

Table 6-91, Figure 6-75, Table 6-92, and Figure 6-76 present timing requirements and switching characteristics for MMC0 – HS400 Mode.

Table 6-91 MMC0 Timing Requirements – HS400 Mode see Figure 6-75

NO.			MIN	MAX	UNIT
HS4000	t_DSMPW	Pulse width, MMC0_DS	1.95		ns
HS4001	t_{RQ_DAT}	Input skew, MMC0_DS to MMC0_DAT valid		475	ps
HS4002	t_{RQH_DAT}	Input skew hold, MMC0_DAT invalid to MMC0_DS		475	ps
HS4003	t_{RQ_CMD}	Input skew, MMC0_DS to MMC0_CMD valid		NA⁽¹⁾	ps
HS4004	t_{RQH_CMD}	Input skew hold, MMC0_CMD invalid to MMC0_DS		NA⁽¹⁾	ps

(1) This parameter is only applicable when operating in Enhanced Strobe mode, which is not supported on this device. The CMD input is captured using an internally delayed version of CLK when not operating in Enhanced Strobe mode, and the delay is selected by a tuning algorithm that optimizes CMD input timing. Therefore, it is not possible to define a specific timing requirement for CMD.

AM62P AM62P-Q1 MMC0 –
HS400 – Receive Mode

Figure 6-75 MMC0 – HS400 – Receive Mode

Table 6-92 MMC0 Switching Characteristics – HS400 Mode see Figure 6-76

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
	f_op(clk)	Operating frequency, MMC0_CLK		200	MHz
HS4005	t_c(clkH)	Cycle time, MMC0_CLK	5.0		ns
HS4006	t_w(clkH)	Pulse duration, MMC0_CLK high	2.30		ns
HS4007	t_w(clkL)	Pulse duration, MMC0_CLK low	2.30		ns
HS4008	t_{osu(cmdV-clkH)}	Output setup time, MMC0_CMD valid to MMC0_CLK rising edge⁽¹⁾	2.86		ns
HS4009	t_osu(dV-clk)	Output setup time, MMC0_DAT[7:0] valid to MMC0_CLK rising or falling edge⁽¹⁾	0.700		ns
HS40010	t_{oh(clkH-cmdIV)}	Output hold time, MMC0_CLK rising edge to MMC0_CMD invalid⁽²⁾	1.16		ns
HS40011	t_oh(clk-dIV)	Output hold time, MMC0_CLK rising or falling edge to MMC0_DAT[7:0] invalid⁽²⁾	0.760		ns

(1) This parameter defines the output setup time provided to the attached device. This time is relative to the next capture clock edge and already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references for this parameter are from mid-supply of the DAT or CMD signal transition to mid-supply of the CLK signal transition. The eMMC standard defines the setup timing references from VIL or VIH of the DAT or CMD signal transition to mid-supply of the CLK signal transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure the time it takes for the DAT signal to slew from mid-supply to VIL or VIH does not erode the setup time margin.

(2) This parameter defines the output hold time provided to the attached device. This time is relative to the previous launch clock edge and already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references for this parameter are from mid-supply of the CLK signal transition to mid-supply of the DAT or CMD signal transition. The eMMC standard defines the hold timing references from mid-supply of the CLK signal transition to VIL or VIH of the DAT or CMD signal transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure the time it takes for the DAT signal to slew from VIL or VIH to mid-supply does not erode the hold time margin.

AM62P AM62P-Q1 eMMC in –
HS400 Mode – Transmitter Mode

Figure 6-76 eMMC in – HS400 Mode – Transmitter Mode