SPRUGR9H November   2010  – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Preface
    1.     About This Manual
    2.     Trademarks
    3.     Notational Conventions
    4.     Related Documentation from Texas Instruments
  2. 1Introduction
    1. 1.1  Terminology Used in This Document
    2. 1.2  KeyStone I Features
    3. 1.3  KeyStone I Functional Block Diagram
    4. 1.4  KeyStone II Changes to QMSS
    5. 1.5  KeyStone II QMSS Modes of Use
      1. 1.5.1 Shared Mode
      2. 1.5.2 Split Mode
    6. 1.6  Overview
    7. 1.7  Queue Manager
    8. 1.8  Packet DMA (PKTDMA)
    9. 1.9  Navigator Cloud
    10. 1.10 Virtualization
    11. 1.11 ARM-DSP Shared Use
    12. 1.12 PDSP Firmware
  3. 2Operational Concepts
    1. 2.1 Packets
    2. 2.2 Queues
      1. 2.2.1 Packet Queuing
      2. 2.2.2 Packet De-queuing
      3. 2.2.3 Queue Proxy
    3. 2.3 Queue Types
      1. 2.3.1 Transmit Queues
      2. 2.3.2 Transmit Completion Queues
      3. 2.3.3 Receive Queues
      4. 2.3.4 Free Descriptor Queues (FDQ)
        1. 2.3.4.1 Host Packet Free Descriptors
        2. 2.3.4.2 Monolithic Free Descriptors
      5. 2.3.5 Queue Pend Queues
    4. 2.4 Descriptors
      1. 2.4.1 Host Packet
      2. 2.4.2 Host Buffer
      3. 2.4.3 Monolithic Packet
    5. 2.5 Packet DMA
      1. 2.5.1 Channels
      2. 2.5.2 RX Flows
    6. 2.6 Packet Transmission Overview
    7. 2.7 Packet Reception Overview
    8. 2.8 ARM Endianess
  4. 3Descriptor Layouts
    1. 3.1 Host Packet Descriptor
    2. 3.2 Host Buffer Descriptor
    3. 3.3 Monolithic Descriptor
  5. 4Registers
    1. 4.1 Queue Manager
      1. 4.1.1 Queue Configuration Region
        1. 4.1.1.1 Revision Register (0x00000000)
        2. 4.1.1.2 Queue Diversion Register (0x00000008)
        3. 4.1.1.3 Linking RAM Region 0 Base Address Register (0x0000000C)
        4. 4.1.1.4 Linking RAM Region 0 Size Register (0x00000010)
        5. 4.1.1.5 Linking RAM Region 1 Base Address Register (0x00000014)
        6. 4.1.1.6 Free Descriptor/Buffer Starvation Count Register N (0x00000020 + N×4)
      2. 4.1.2 Queue Status RAM
      3. 4.1.3 Descriptor Memory Setup Region
        1. 4.1.3.1 Memory Region R Base Address Register (0x00000000 + 16×R)
        2. 4.1.3.2 Memory Region R Start Index Register (0x00000004 + 16×R)
        3. 4.1.3.3 Memory Region R Descriptor Setup Register (0x00000008 + 16×R)
      4. 4.1.4 Queue Management/Queue Proxy Regions
        1. 4.1.4.1 Queue N Register A (0x00000000 + 16×N)
        2. 4.1.4.2 Queue N Register B (0x00000004 + 16×N)
        3. 4.1.4.3 Queue N Register C (0x00000008 + 16×N)
        4. 4.1.4.4 Queue N Register D (0x0000000C + 16×N)
      5. 4.1.5 Queue Peek Region
        1. 4.1.5.1 Queue N Status and Configuration Register A (0x00000000 + 16×N)
        2. 4.1.5.2 Queue N Status and Configuration Register B (0x00000004 + 16×N)
        3. 4.1.5.3 Queue N Status and Configuration Register C (0x00000008 + 16×N)
        4. 4.1.5.4 Queue N Status and Configuration Register D (0x0000000C + 16×N)
    2. 4.2 Packet DMA
      1. 4.2.1 Global Control Registers Region
        1. 4.2.1.1 Revision Register (0x00)
        2. 4.2.1.2 Performance Control Register (0x04)
        3. 4.2.1.3 Emulation Control Register (0x08)
        4. 4.2.1.4 Priority Control Register (0x0C)
        5. 4.2.1.5 QMn Base Address Register (0x10, 0x14, 0x18, 0x1c)
      2. 4.2.2 TX DMA Channel Configuration Region
        1. 4.2.2.1 TX Channel N Global Configuration Register A (0x000 + 32×N)
        2. 4.2.2.2 TX Channel N Global Configuration Register B (0x004 + 32×N)
      3. 4.2.3 RX DMA Channel Configuration Region
        1. 4.2.3.1 RX Channel N Global Configuration Register A (0x000 + 32×N)
      4. 4.2.4 RX DMA Flow Configuration Region
        1. 4.2.4.1 RX Flow N Configuration Register A (0x000 + 32×N)
        2. 4.2.4.2 RX Flow N Configuration Register B (0x004 + 32×N)
        3. 4.2.4.3 RX Flow N Configuration Register C (0x008 + 32×N)
        4. 4.2.4.4 RX Flow N Configuration Register D (0x00C + 32×N)
        5. 4.2.4.5 RX Flow N Configuration Register E (0x010 + 32×N)
        6. 4.2.4.6 RX Flow N Configuration Register F (0x014 + 32×N)
        7. 4.2.4.7 RX Flow N Configuration Register G (0x018 + 32×N)
        8. 4.2.4.8 RX Flow N Configuration Register H (0x01C + 32×N)
      5. 4.2.5 TX Scheduler Configuration Region
        1. 4.2.5.1 TX Channel N Scheduler Configuration Register (0x000 + 4×N)
    3. 4.3 QMSS PDSPs
      1. 4.3.1 Descriptor Accumulation Firmware
        1. 4.3.1.1 Command Buffer Interface
        2. 4.3.1.2 Global Timer Command Interface
        3. 4.3.1.3 Reclamation Queue Command Interface
        4. 4.3.1.4 Queue Diversion Command Interface
      2. 4.3.2 Quality of Service Firmware
        1. 4.3.2.1 QoS Algorithms
          1. 4.3.2.1.1 Modified Token Bucket Algorithm
        2. 4.3.2.2 Command Buffer Interface
        3. 4.3.2.3 QoS Firmware Commands
        4. 4.3.2.4 QoS Queue Record
        5. 4.3.2.5 QoS Cluster Record
        6. 4.3.2.6 RR-Mode QoS Cluster Record
        7. 4.3.2.7 SRIO Queue Monitoring
          1. 4.3.2.7.1 QoS SRIO Queue Monitoring Record
      3. 4.3.3 Open Event Machine Firmware
      4. 4.3.4 Interrupt Operation
        1. 4.3.4.1 Interrupt Handshaking
        2. 4.3.4.2 Interrupt Processing
        3. 4.3.4.3 Interrupt Generation
        4. 4.3.4.4 Stall Avoidance
      5. 4.3.5 QMSS PDSP Registers
        1. 4.3.5.1 Control Register (0x00000000)
        2. 4.3.5.2 Status Register (0x00000004)
        3. 4.3.5.3 Cycle Count Register (0x0000000C)
        4. 4.3.5.4 Stall Count Register (0x00000010)
    4. 4.4 QMSS Interrupt Distributor
      1. 4.4.1 INTD Register Region
        1. 4.4.1.1  Revision Register (0x00000000)
        2. 4.4.1.2  End Of Interrupt (EOI) Register (0x00000010)
        3. 4.4.1.3  Status Register 0 (0x00000200)
        4. 4.4.1.4  Status Register 1 (0x00000204)
        5. 4.4.1.5  Status Register 2 (0x00000208)
        6. 4.4.1.6  Status Register 3 (0x0000020c)
        7. 4.4.1.7  Status Register 4 (0x00000210)
        8. 4.4.1.8  Status Clear Register 0 (0x00000280)
        9. 4.4.1.9  Status Clear Register 1 (0x00000284)
        10. 4.4.1.10 Status Clear Register 4 (0x00000290)
        11. 4.4.1.11 Interrupt N Count Register (0x00000300 + 4xN)
  6. 5Mapping Information
    1. 5.1 Queue Maps
    2. 5.2 Interrupt Maps
      1. 5.2.1 KeyStone I TCI661x, C6670, C665x devices
      2. 5.2.2 KeyStone I TCI660x, C667x devices
      3. 5.2.3 KeyStone II devices
    3. 5.3 Memory Maps
      1. 5.3.1 QMSS Register Memory Map
      2. 5.3.2 KeyStone I PKTDMA Register Memory Map
      3. 5.3.3 KeyStone II PKTDMA Register Memory Map
    4. 5.4 Packet DMA Channel Map
  7. 6Programming Information
    1. 6.1 Programming Considerations
      1. 6.1.1 System Planning
      2. 6.1.2 Notification of Completed Work
    2. 6.2 Example Code
      1. 6.2.1 QMSS Initialization
      2. 6.2.2 PKTDMA Initialization
      3. 6.2.3 Normal Infrastructure DMA with Accumulation
      4. 6.2.4 Bypass Infrastructure notification with Accumulation
      5. 6.2.5 Channel Teardown
    3. 6.3 Programming Overrides
    4. 6.4 Programming Errors
    5. 6.5 Questions and Answers
  8. AExample Code Utility Functions
  9. BExample Code Types
  10. CExample Code Addresses
    1. C.1 KeyStone I Addresses:
    2. C.2 KeyStone II Addresses:
  11.   Revision History

3.3 Monolithic Descriptor

The monolithic packet descriptor contains the following information:

  • Indicator that identifies the descriptor as a monolithic packet descriptor
  • Source and destination tags
  • Packet type
  • Packet length
  • Packet error indicator
  • Packet return information
  • Protocol-specific region size
  • Protocol-specific region offset
  • Protocol-specific control / status bits
  • Packet data

The maximum size of a monolithic packet descriptor is 65535 bytes. Of this, monolithic packet descriptors always contain 12 bytes of required information and may also contain 16 bytes of software-specific tagging information and up to 128 bytes (indicated in 4-byte increments) of protocol-specific information. How much protocol-specific information (and therefore the allocated size of the descriptors) is application dependent. The descriptor layout is shown in Table 3-24.

Table 3-24 Monolithic Packet Descriptor Layout

Packet info (12 bytes)
Extended packet info block (optional)
Includes PS bits, timestamp, and SW data words
(20 bytes)
Protocol-Specific data (optional)
(0 to M bytes where M is a multiple of 4)
Null region (0 to (511-12) bytes)
Packet data
(0 to 64K – 1)
Other SW data (optional and user defined)
Packet info (12 bytes)
Extended packet info block (optional)
Includes PS bits, timestamp, and SW data words
(20 bytes)
Protocol-Specific data (optional)
(0 to M bytes where M is a multiple of 4)
Null region (0 to (511-12) bytes)
Packet data
(0 to 64K – 1)
Other SW data (optional and user defined)

The other SW data portion of the descriptor exists after all of the defined words and is reserved for use by the host software to store private data. This region is not used in any way by the DMA or queue manager modules in a Multicore Navigator system and these modules will not modify any bytes within this region.

A note on the placement of data with respect to the optional EPIB block: If EPIB is present, the 16 bytes of EPIB data begins at byte offset 16, and PS or packet data may begin at byte offset 32 (from the descriptor address). If EPIB is not present, PS or packet data may begin at byte offset 12 (from the descriptor address).

The contents of the monolithic packet descriptor words are detailed in the following tables:

Table 3-25 Monolithic Packet Descriptor Word 0

Bits Name Description RX Overwrite
31-30 Packet Id Monolithic packet descriptor type. Value is always 2 (0x02) for monolithic descriptors. Yes
29-25 Packet Type This field indicates the type of this packet and is encoded as follows:
  • 0-31 = To Be Assigned
Yes
24-16 Data Offset This field indicates the byte offset from byte 0 of this descriptor to the location where the valid data begins.

On RX, this value is set equal to the value for the SOP offset given in the RX DMA channel’s monolithic control register.

When a monolithic packet is processed, this value may be modified in order to add or remove bytes to or from the beginning of the packet.

The value for this field can range from 0-511 bytes, which means that the maximum NULL region can be 511-12 bytes, because byte 0 is the start of the 12 byte packet info area.

Note that the value of this field must always be greater than or equal to 4 times the value given in the Protocol Specific Valid Word Count field.

 Yes
15-0 Packet Length The length of the packet data in bytes. The valid range is from 0 to 65535 bytes. NOTE: The sum of the data offset field and the packet length must not exceed 64KB or the defined size of the descriptor. To do so is an error, and may cause transmission problems through the Streaming Interface. Yes

Table 3-26 Monolithic Packet Descriptor Word 1

Bits Name Description RX Overwrite
31-24 Source Tag - Hi This field is application-specific. During packet reception, the DMA controller in the port will overwrite this field as specified in the RX_SRC_TAG_HI_SEL field in the flow configuration table entry. Configurable
23-16 Source Tag - Lo This field is application-specific. During packet reception, the DMA controller in the port will overwrite this field as specified in the RX_SRC_TAG_LO_SEL field in the flow configuration table entry. For TX, this value supplies the RX flow index to the streaming I/F for infrastructure use. Configurable
15-8 Dest Tag – Hi This field is application-specific. During packet reception, the DMA controller in the port will overwrite this field as specified in the RX_DEST_TAG_HI_SEL field in the flow configuration table entry. Configurable
7-0 Dest Tag - Lo This field is application-specific. During packet reception, the DMA controller in the port will overwrite this field as specified in the RX_DEST_TAG_LO_SEL field in the flow configuration table entry. Configurable

Table 3-27 Monolithic Packet Descriptor Word 2

Bits Name Description RX Overwrite
31 Extended Packet Info Block Present This field indicates the presence of the extended packet info block in the descriptor.
  • 0 = EPIB is not present
  • 1 = 16 byte EPIB is present
 Yes
30 Reserved Unused Yes
29-24 Protocol Specific Valid Word Count This field indicates the valid number of 32-bit words in the protocol-specific region. This is encoded in increments of 4 bytes as follows:
  • 0 = 0 bytes
  • 1 = 4 bytes
  • …
  • 16 = 64 bytes
  • …
  • 32 = 128 bytes
  • 33-63 = Reserved
 Yes
23-20 Error Flags This field contains error flags that can be assigned based on the packet type. Yes
19-16 Protocol Specific Flags This field contains protocol-specific flags / information that can be assigned based on the packet type. Yes
15 Reserved Unused No
14 Return Push Policy This field indicates how a transmit DMA should return the descriptor pointers to the free queues. This field is encoded as follows:
  • 0 = Descriptor must be returned to tail of queue
  • 1 = Descriptor must be returned to head of queue
 No
13-12 Packet Return Queue Mgr # This field indicates which of the four potential queue managers in the system the descriptor is to be returned to after transmission is complete. This field is not altered by the DMA during transmission or reception and should be initialized by the host. No
11-0 Packet Return Queue # This field indicates the queue number within the selected queue manager that the descriptor is to be returned to after transmission is complete. No

Table 3-28 Monolithic Extended Packet NULL Word (Optional) (1)

Bits Name Description RX Overwrite
31-0 Reserved This field is present only to align the extended packet words to a 128-bit boundary in memory. This word can be used for host SW scratchpad because it will not be copied or overwritten by the DMA components. No
(1) This word is present only if the Extended Packet Info Block present bit is set in word 2.

Table 3-29 Monolithic Extended Packet Info Word 0 (Optional) (1)

Bits Name Description RX Overwrite
31-0 Timestamp Info This field contains an application-specific timestamp that can be used for traffic shaping in a QoS-enabled system. Configurable
(1) This word is present only if the Extended Packet Info Block present bit is set in word 2.

Table 3-30 Monolithic Extended Packet Info Word 1 (Optional) (1)

Bits Name Description RX Overwrite
31-0 Software Info 0 This field stores software-centric information that needs to travel with the packet through the stack. This information will be copied from the source descriptor to the destination descriptor whenever a prefetch operation is performed or when transferring through an infrastructure DMA node. Configurable
(1) This word is present only if the Extended Packet Info Block present bit is set in word 2.

Table 3-31 Monolithic Extended Packet Info Word 2 (Optional) (1)

Bits Name Description RX Overwrite
31-0 Software Info 1 This field stores software-centric information that needs to travel with the packet through the stack. This information will be copied from the source descriptor to the destination descriptor whenever a prefetch operation is performed or when transferring through an infrastructure DMA node. Configurable
(1) This word is present only if the Extended Packet Info Block present bit is set in word 2.

Table 3-32 Monolithic Extended Packet Info Word 3 (Optional) (1)

Bits Name Description RX Overwrite
31-0 Software Info 2 This field stores software-centric information that needs to travel with the packet through the stack. This information will be copied from the source descriptor to the destination descriptor whenever a prefetch operation is performed or when transferring through an infrastructure DMA node. Configurable
(1) This word is present only if the Extended Packet Info Block present bit is set in word 2.

Table 3-33 Monolithic Packet Descriptor Protocol Specific Word M (Optional) (1)

Bits Name Description RX Overwrite
31-0 Protocol Specific Data N This field stores information that varies depending on the packet type. Configurable
(1) These words, if present, immediately follow the software data block information.

Table 3-34 Monolithic Packet Descriptor Payload Data Words 0-N (1)(2)

Bits Name Description RX Overwrite
31-0 Packet Data N These words store the packet payload data. Yes
(1) The payload data follows the protocol-specific words at an offset specified in the data offset field of word 0.
(2) This field is endian-specific. In other words, this is the only field in the descriptor that changes based on the endianess of the system.