Eight SM320C66x DSP Core Subsystems at 1.00 GHz
- 32KB L1P, 32KB L1D, 512KB L2 Per Core
- 4MB Shared L2
Multicore Navigator and TeraNet Switch Fabric - 2 Tb
Network Coprocessors- Packet Accelerator, Security Accelerator
Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex
Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex
HyperLink - Up to 50Gbaud Operation at -40C to 105C and 25 GBaud at -55C to 115C, Full Duplex
Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation
64-Bit DDR3 Interface (DDR3-1600) - 8 GByte Addressable Memory Space
16-Bit EMIF - Async SRAM, NAND and NOR Flash Support
Two Telecom Serial Ports (TSIP) - 2/4/8 Lanes at 32.768/16.384/8.192
UART Interface
I2C Interface
16 GPIO Pins
SPI Interface
Sixteen 64-Bit Timers
Three On-Chip PLLs

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The SM320C6678 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with eight C66x CorePac DSPs, each core runs at 1.0 GHz enabling up to 8 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6678 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

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Technical documentation

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	Type	Title	Date
*	Datasheet	SM320C6678-HIREL Multicore Fixed and Floating-Point Digital Signal Processor datasheet (Rev. A)	Apr. 03, 2014
*	Errata	TMS320C6678 Multcore Fixed & Floating-Point DSP Silicon Errata (Revs 1.0, 2.0) (Rev. H)	Jun. 29, 2015
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)	Jun. 01, 2020
	Application note	Hardware Design Guide for KeyStone Devices (Rev. D)	Mar. 21, 2019
	Technical articles	Bringing the next evolution of machine learning to the edge	Nov. 27, 2018
	Technical articles	Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet	Oct. 30, 2018
	Technical articles	How quality assurance on the Processor SDK can improve software scalability	Aug. 22, 2018
	Application note	DDR3 Design Requirements for KeyStone Devices (Rev. C)	Jan. 23, 2018
	Application note	Thermal Design Guide for DSP and Arm Application Processors (Rev. B)	Aug. 14, 2017
	User guide	Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)	Jul. 26, 2017
	Application note	KeyStone I DDR3 Initialization (Rev. E)	Oct. 28, 2016
	Technical articles	Clove: Low-Power video solutions based on Sitara™ AM57x processors	Jul. 21, 2016
	User guide	Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)	May 06, 2015
	User guide	Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)	Apr. 09, 2015
	User guide	DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)	Jan. 20, 2015
	User guide	Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)	Sep. 04, 2014
	User guide	Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)	Sep. 03, 2014
	User guide	System Analyzer User's Guide (Rev. F)	Nov. 18, 2013
	User guide	PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)	Sep. 30, 2013
	User guide	DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)	Jul. 15, 2013
	White paper	Another Look at the Future of Medical Processing	Jul. 12, 2013
	White paper	Medical Software Development on Keystone Devices	Jul. 12, 2013
	White paper	Accelerating high-performance computing development with Desktop Linux SDK	Jul. 08, 2013
	User guide	Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)	Jul. 03, 2013
	User guide	C66x CorePac User's Guide (Rev. C)	Jun. 28, 2013
	User guide	Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)	Jun. 28, 2013
	User guide	HyperLink for KeyStone Devices User's Guide (Rev. C)	May 28, 2013
	User guide	Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)	Feb. 05, 2013
	More literature	Multicore DSPs for High-Performance Video Coding	Jan. 22, 2013
	More literature	OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A)	Nov. 05, 2012
	Application note	SerDes Implementation Guidelines for KeyStone I Devices	Oct. 31, 2012
	More literature	TMS320C66x high-performance multicore DSPs for video surveillance	Sep. 06, 2012
	Application note	Multicore Programming Guide (Rev. B)	Aug. 29, 2012
	User guide	TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)	Aug. 21, 2012
	User guide	TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)	Aug. 21, 2012
	User guide	Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)	Jul. 11, 2012
	White paper	Leveraging multicore processors for machine vision applications	May 09, 2012
	User guide	Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)	Apr. 24, 2012
	More literature	TMS320C6678 Multicore DSP for Multimedia Infrastructure (Rev. A)	Apr. 11, 2012
	User guide	Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)	Mar. 30, 2012
	User guide	Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)	Mar. 27, 2012
	User guide	64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)	Mar. 22, 2012
	White paper	Maximizing Multicore Efficiency with Navigator Runtime	Feb. 23, 2012
	White paper	Comparing TI's TMS320C6671 DSP with ADI’s ADSP-TS201S TigerSHARC Processor (Rev. A)	Jan. 06, 2012
	Application note	PCIe Use Cases for KeyStone Devices	Dec. 13, 2011
	User guide	Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)	Oct. 15, 2011
	Application note	Introduction to TMS320C6000 DSP Optimization	Oct. 06, 2011
	User guide	Debug and Trace for KeyStone I Devices User's Guide (Rev. A)	Sep. 22, 2011
	User guide	Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide	Sep. 02, 2011
	White paper	KeyStone Multicore SoC Tool Suite: one platform for all needs	Jun. 17, 2011
	User guide	External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)	May 24, 2011
	White paper	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market	May 19, 2011
	More literature	TMS320C6671/72/74/78 High-Performance Multicore Fixed- and Floating-Point DSPs (Rev. B)	Apr. 25, 2011
	Application note	TMS320C66x DSP Generation of Devices (Rev. A)	Apr. 25, 2011
	White paper	Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP	Mar. 16, 2011
	White paper	Software-Based Ultrasound Beamforming on Multicore DSPs	Mar. 06, 2011
	White paper	KeyStone Memory Architecture White Paper (Rev. A)	Dec. 21, 2010
	User guide	C66x CPU and Instruction Set Reference Guide	Nov. 09, 2010
	User guide	C66x DSP Cache User's Guide	Nov. 09, 2010
	Application note	Clocking Design Guide for KeyStone Devices	Nov. 09, 2010
	User guide	General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide	Nov. 09, 2010
	Application note	Optimizing Loops on the C66x DSP	Nov. 09, 2010
	User guide	Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide	Nov. 09, 2010
	User guide	Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG	Nov. 09, 2010
	User guide	Network Coprocessor for KeyStone Devices User's Guide	Nov. 02, 2010

Design & development

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Hardware development

DEBUG PROBE Download

XDS200 USB Debug Probe

TMDSEMU200-U

295

Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

SM320C6678-HIREL

Multicore Fixed and Floating-Point Digital Signal Processor