Product details


DSP 2 C66x DSP MHz (Max) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (C) -40 to 100, 0 to 85 open-in-new Find other Digital signal processors (DSPs)


  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C
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The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

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Technical documentation

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Type Title Date
* Data sheet TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. D) Sep. 04, 2019
* Errata TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) May 19, 2016
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) Jun. 25, 2021
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) May 19, 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling Jun. 11, 2019
Application note Keystone Bootloader Resources and FAQ May 29, 2019
Application note Keystone Multicore Device Family Schematic Checklist May 17, 2019
Application note Hardware Design Guide for KeyStone Devices (Rev. D) Mar. 21, 2019
Application note KeyStone I DDR3 interface bring-up Mar. 06, 2019
Technical article Bringing the next evolution of machine learning to the edge Nov. 27, 2018
Technical article Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet Oct. 30, 2018
Technical article How quality assurance on the Processor SDK can improve software scalability Aug. 22, 2018
White paper Designing professional audio mixers for every scenario Jun. 28, 2018
Application note DDR3 Design Requirements for KeyStone Devices (Rev. C) Jan. 23, 2018
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug. 14, 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul. 26, 2017
Application note PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A) May 19, 2017
Application note Processor SDK RTOS Audio Benchmark Starter Kit Apr. 12, 2017
Application note Power Consumption Summary for KeyStone C66x Devices (Rev. B) Feb. 02, 2017
Application note KeyStone I DDR3 Initialization (Rev. E) Oct. 28, 2016
Application note Keystone NDK FAQ Oct. 03, 2016
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors Jul. 21, 2016
More literature TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) May 23, 2016
Application note SERDES Link Commissioning on KeyStone I and II Devices Apr. 13, 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs Feb. 23, 2016
Application note TI DSP Benchmarking Jan. 13, 2016
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug. 13, 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) May 06, 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) Apr. 09, 2015
White paper TI’s processors leading the way in embedded analytics Mar. 03, 2015
User guide DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) Jan. 20, 2015
Application note TI Keystone DSP Hyperlink SerDes IBIS-AMI Models Oct. 09, 2014
Application note TI Keystone DSP PCIe SerDes IBIS-AMI Models Oct. 09, 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep. 04, 2014
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) Sep. 03, 2014
More literature KeyStone Lab Manual - Training Jun. 05, 2014
User guide System Analyzer User's Guide (Rev. F) Nov. 18, 2013
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) Sep. 30, 2013
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) Jul. 15, 2013
White paper Accelerating high-performance computing development with Desktop Linux SDK Jul. 08, 2013
User guide C66x CorePac User's Guide (Rev. C) Jun. 28, 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun. 28, 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) May 28, 2013
More literature OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) Nov. 05, 2012
Application note SerDes Implementation Guidelines for KeyStone I Devices Oct. 31, 2012
More literature TMS320C66x high-performance multicore DSPs for video surveillance Sep. 06, 2012
Application note Multicore Programming Guide (Rev. B) Aug. 29, 2012
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug. 21, 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug. 21, 2012
User guide Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices Jul. 12, 2012
User guide Universal Parallel Port (uPP) for KeyStone Architecture User's Guide Jun. 11, 2012
User guide Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices May 25, 2012
White paper Leveraging multicore processors for machine vision applications May 09, 2012
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) Apr. 24, 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar. 30, 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar. 27, 2012
White paper Superior performance at breakthrough size, weight & power Mar. 26, 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar. 22, 2012
White paper Maximizing Multicore Efficiency with Navigator Runtime Feb. 23, 2012
Application note PCIe Use Cases for KeyStone Devices Dec. 13, 2011
User guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) Oct. 15, 2011
Application note Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guide Debug and Trace for KeyStone I Devices User's Guide (Rev. A) Sep. 22, 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep. 02, 2011
White paper KeyStone Multicore SoC Tool Suite: one platform for all needs Jun. 17, 2011
User guide Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A) Jun. 10, 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
Application note TMS320C66x DSP Generation of Devices (Rev. A) Apr. 25, 2011
White paper Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP Mar. 16, 2011
White paper Software-Based Ultrasound Beamforming on Multicore DSPs Mar. 06, 2011
White paper KeyStone Memory Architecture White Paper (Rev. A) Dec. 21, 2010
User guide Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide Nov. 18, 2010
User guide C66x CPU and Instruction Set Reference Guide Nov. 09, 2010
User guide C66x DSP Cache User's Guide Nov. 09, 2010
Application note Clocking Design Guide for KeyStone Devices Nov. 09, 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov. 09, 2010
Application note Optimizing Loops on the C66x DSP Nov. 09, 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov. 09, 2010
User guide Flip Chip Ball Grid Array Package Reference Guide (Rev. A) May 23, 2005
Application note AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) May 01, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The TMS3206657 Lite Evaluation Module (EVM), is an easy-to-use, cost-efficient development tool that helps developers quickly get started with designs using the C6657 or C6655 or C6654 family of DSPs. The EVM includes an on-board, single C6657 processor with robust connectivity options that allows (...)

eInfochips System on Modules and EVMs
Provided by eInfochips

eInfochips is a product engineering and design services company with over 20 years of experience, 500+ product developments, and over 40M deployments in 140 countries, across the world. The company has delivered turnkey technology solutions for many Fortune 500 companies, across multiple verticals (...)

Sheldon DSP-FPGA boards
Provided by Sheldon Instruments, Inc.
Sheldon Instruments designs and manufactures DSP based, COTS data acquisition and control hardware for PCIe/PCI, PCI104e/PCI104, XMC/PMC, and CompactPCI systems, along with drivers and real time development software for a variety of applications and markets.

Learn more about Sheldon Instruments at (...)
XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)


The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)


The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)


The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

Processor SDK for C665x Processors - TI-RTOS support
PROCESSOR-SDK-C665X Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)


RTOS features:

  • Full driver availability
  • Debug and instrumentation utilities
  • Board support package
  • Demonstrations and examples
  • Code Composer Studio™ IDE for RTOS development
  • Documentation

The Processor SDK is free, and does not require any run-time royalties to Texas Instruments.


DSP Math Library for Floating Point Devices
MATHLIB — The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
  • Types of functions included:
    • Trigonometric and hyperbolic: Sin, Cos, Tan, Arctan, etc.
    • Power, exponential, and logarithmic
    • Reciprocal
    • Square root
    • Division
  • Natural C Source Code
  • Optimized C code with Intrinsics
  • Hand-coded assembly-optimized routines
  • C-callable routines, which can be inlined and are fully (...)
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)


  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  


  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Multicore Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

CODECS- Video, Speech - for C66x-based Devices
C66XCODECS TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
  • Field-hardened and tested
  • LINUX and WINDOWS installers
  • XDC packaged and validated on a standard EVM in a Codec Engine-based test
  • Both encoder and decoder are available
  • All codecs are eXpressDSP™ compliant and implement one of the XDM 1.x interfaces
  • Performance data specified in each codec Datasheet
Encode (...)
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SPRM570.ZIP (415 KB) - IBIS Model
SPRM572.ZIP (21 KB) - BSDL Model
SPRM600.ZIP (178 KB) - Power Model
SPRM742.ZIP (969314 KB) - IBIS Model
Arm-based MPU, arm-based MCU and DSP third-party search tool
PROCESSORS-3P-SEARCH TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
  • Supports many TI processors including Sitara and Jacinto processors and DSPs
  • Search by type of product, TI devices supported, or country
  • Links and contacts for quick engagement
  • Third-party companies located around the world
SPRR178.ZIP (12 KB)
SPRR183.ZIP (3 KB)

Reference designs

Audio Preprocessing System Reference Design for Voice-Based Applications
TIDEP-0099 — This reference design uses multiple microphones, a beamforming algorithm, and other processes to extract clear speech and audio amidst noise and other clutter.  The rapid increase in applications that are used in noise-prone environments for voice activated digital assistants creates demand for (...)
document-generic Schematic
Implementing a Real-time Synthetic Aperture Radar (SAR) Algorithm on TI’s C6678 DSP Reference Design
TIDEP0045 This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
document-generic Schematic
Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
TIDEP0036 The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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Support & training

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