Product details


DSP 1 C66x On-chip L2 cache/RAM 1024 KB Other on-chip memory 1024 KB Total on-chip memory (KB) 1088 Operating system TI-RTOS DRAM DDR3 Serial I/O I2C, SPI, UART, UPP I2C 1 SPI 1 Operating temperature range (C) -40 to 100, 0 to 85 UART (SCI) 2 Rating Catalog open-in-new Find other C6000 floating-point DSPs


  • One TMS320C66x DSP Core Subsystem (CorePac)
    • C66x Fixed- and Floating-Point CPU Core: Up to 850 MHz for C6654 and 600 MHz for C6652
  • Multicore Shared Memory Controller (MSMC)
    • Memory Protection Unit for DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Peripherals
    • PCIe Gen2 (C6654 Only)
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • Gigabit Ethernet (GbE) Subsystem (C6654 Only)
      • One SGMII Port (C6654 Only)
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1066
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

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open-in-new Find other C6000 floating-point DSPs


The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including PCI Express Gen2 and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 55
Type Title Date
* Datasheet TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. E) Sep. 04, 2019
* Errata TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) May 19, 2016
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
Application notes How to Migrate CCS 3.x Projects to the Latest CCS Feb. 06, 2020
Application notes Keystone Error Detection and Correction EDC ECC Aug. 12, 2019
Application notes Using DSPLIB FFT Implementation for Real Input and Without Data Scaling Jun. 11, 2019
Application notes Keystone Bootloader Resources and FAQ May 29, 2019
Application notes Keystone Multicore Device Family Schematic Checklist May 17, 2019
Application notes Hardware Design Guide for KeyStone Devices (Rev. D) Mar. 21, 2019
Application notes KeyStone I DDR3 interface bring-up Mar. 06, 2019
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. U) Feb. 07, 2018
Application notes DDR3 Design Requirements for KeyStone Devices (Rev. C) Jan. 23, 2018
Application notes Thermal Design Guide for DSP and Arm Application Processors (Rev. B) Aug. 14, 2017
User guides Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) Jul. 26, 2017
Application notes KeyStone I DDR3 Initialization (Rev. E) Oct. 28, 2016
More literature TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) May 23, 2016
Application notes TI DSP Benchmarking Jan. 13, 2016
Application notes Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug. 13, 2015
Technical articles “Swiss Army Knife” of audio codecs Jun. 26, 2015
User guides Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) May 06, 2015
User guides Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) Apr. 09, 2015
User guides DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) Jan. 20, 2015
User guides Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) Sep. 04, 2014
More literature KeyStone Lab Manual - Training Jun. 05, 2014
User guides System Analyzer User's Guide (Rev. F) Nov. 18, 2013
User guides DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) Jul. 15, 2013
White papers Accelerating high-performance computing development with Desktop Linux SDK Jul. 08, 2013
User guides C66x CorePac User's Guide (Rev. C) Jun. 28, 2013
User guides Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) Jun. 28, 2013
More literature OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) Nov. 05, 2012
More literature TMS320C66x high-performance multicore DSPs for video surveillance Sep. 06, 2012
User guides Universal Parallel Port (uPP) for KeyStone Architecture User's Guide Jun. 11, 2012
User guides Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices May 25, 2012
White papers Leveraging multicore processors for machine vision applications May 09, 2012
User guides Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) Mar. 30, 2012
User guides Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) Mar. 27, 2012
White papers Superior performance at breakthrough size, weight & power Mar. 26, 2012
User guides 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) Mar. 22, 2012
User guides Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) Oct. 15, 2011
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides Debug and Trace for KeyStone I Devices User's Guide (Rev. A) Sep. 22, 2011
User guides Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide Sep. 02, 2011
White papers KeyStone Multicore SoC Tool Suite: one platform for all needs Jun. 17, 2011
User guides External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) May 24, 2011
White papers Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
Application notes TMS320C66x DSP Generation of Devices (Rev. A) Apr. 25, 2011
White papers KeyStone Memory Architecture White Paper (Rev. A) Dec. 21, 2010
User guides C66x CPU and Instruction Set Reference Guide Nov. 09, 2010
User guides C66x DSP Cache User's Guide Nov. 09, 2010
Application notes Clocking Design Guide for KeyStone Devices Nov. 09, 2010
User guides General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide Nov. 09, 2010
Application notes Optimizing Loops on the C66x DSP Nov. 09, 2010
User guides Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG Nov. 09, 2010
User guides Flip Chip Ball Grid Array Package Reference Guide (Rev. A) May 23, 2005
Application notes AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) May 01, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The TMS3206657 Lite Evaluation Module (EVM), is an easy-to-use, cost-efficient development tool that helps developers quickly get started with designs using the C6657 or C6655 or C6654 family of DSPs. The EVM includes an on-board, single C6657 processor with robust connectivity options that allows (...)

Sheldon DSP-FPGA boards
Provided by Sheldon Instruments, Inc.
Sheldon Instruments designs and manufactures DSP based, COTS data acquisition and control hardware for PCIe/PCI, PCI104e/PCI104, XMC/PMC, and CompactPCI systems, along with drivers and real time development software for a variety of applications and markets.

Learn more about Sheldon Instruments at (...)

Software development

Processor SDK for C665x Processors - TI-RTOS support
PROCESSOR-SDK-C665X Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)


RTOS features:

  • Full driver availability
  • Debug and instrumentation utilities
  • Board support package
  • Demonstrations and examples
  • Code Composer Studio™ IDE for RTOS development
  • Documentation

The Processor SDK is free, and does not require any run-time royalties to Texas Instruments.


C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SPRM676.ZIP (176 KB) - Power Model

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