SPRUJ10E May   2022  – May 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  6. 2Kit Overview
    1. 3.1 Introduction
    2. 3.2 Kit Contents
    3. 3.3 Specification
      1. 3.3.1 Key Features
      2. 3.3.2 Component Identification
      3. 3.3.3 Functional Block Diagram
    4. 3.4 Device Information
    5. 3.5 BoosterPacks
    6. 3.6 Compliance
    7. 3.7 Security
  7. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
  8. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 5.6.2 Ethernet PHY #2: CPSW RGMII/ICSSM
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 EQEP and SDFM
    19. 5.19 EPWM
    20. 5.20 BoosterPack Headers
    21. 5.21 Pinmux Mapping
  9. 5EVM Revision Design Changes
    1. 6.1 Rev A Design Changes
  10. 6Hardware Design Files
  11. 7References
    1. 8.1 Reference Documents
    2. 8.2 Other TI Components Used in This Design
  12.   Trademarks
  13. 8Revision History

3.3 Boot Mode Selection

The bootmode for the AM263x is selected by a DIP switch (SW1) or the test automation header. The test automation header uses an I2C expansion buffer to drive the bootmode when PORz is toggled. The supported boot modes are shown in Table 3-6. The DIP Switch configurations for each bootmode are shown in Table 3-5.

Bootmode DIP Switch Positions Figure 3-6 Bootmode DIP Switch Positions
Table 3-5 Boot-Mode Selection
Boot Mode SPI0_D0_pad (SOP3) SPI0_CLK_pad (SOP2) QSPI_D1 (SOP1) QSPI_D0 (SOP0)
QSPI (4S) - Quad Read Mode 1 1 1 1
UART 1 1 1 0
QSPI (1S) - Single Read Mode 1 1 0 1
QSPI (4S) - Quad Read UART Fallback Mode 1 0 1 1
QSPI (1S) - Single Read UART Fallback Mode 1 0 1 0
DevBoot 0 1 0 0
Unsupported Boot Mode All other combinations not defined above
Table 3-6 Supported Boot Modes
Boot Mode/Peripheral Boot Media/Host Notes
QSPI (4S) - Quad Read Mode QSPI Flash Download and boot SBL from QSPI flash in quad read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
UART External Host Download and boot SBL from UART. Device is expected to get SBL from UART. Device supports the XMODEM protocol for download over UART.
QSPI (1S) - Single Read Mode QSPI Flash Download and boot SBL from QSPI flash in single read mode. Attempt Primary SBL,followed by Secondary SBL if primary loading fails.
QSPI (4S) - Quad Read UART Fallback Mode QSPI Flash / External Host Download and boot SBL from QSPI flash in quad read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails. If Secondary SBL also fails then boot from external host via UART interface.
QSPI (1S) - Single Read UART Fallback Mode QSPI Flash / External Host Download and boot SBL from QSPI flash in single read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails. If Secondary SBL also fails then boot from external host via UART interface.
DevBoot N/A No SBL. Used for development purposes only.