SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.16 Test Automation Interface

The LaunchPad supports a 40-pin test automation header (687140183622 from Wurth) that allows an external controller to manipulate some basic operations like power down, power on reset (POR), warm reset, boot mode control and other functions.

GUID-20210719-CA0I-2CLR-K6KL-NXTGNCJ8MMDR-low.png Figure 4-28 Test Automation Header
Table 4-20 Test Automation Signal Description
Signal Signal Type Function
POWER_DOWN GPIO Instructs the LaunchPad to power down all circuits
PORZn GPIO Creates a PORz into the AM243x
WARM_RESETn GPIO Creates a RESETz into the AM243x
GPIO3 GPIO Disables the boot mode buffer
GPIO4 GPIO Resets the bootmode IO expander
Bootmode_I2C I2C communicates with bootmode I2C buffer
I2C1 I2C For internal testing

The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages used by the AM243x. Boot mode for the AM243x can be controlled by either the DIP switch or the test automation header through the I2C IO expander.

A boot mode buffer (SN74AVC8T245RHL) is used to isolate the boot mode controls that are driven through either the DIP switch or the I2C IO expander. The test automation circuit is powered by an always on supply that is generated from a dedicated regulator (TPS7A0533PDBVT).

The test automation header supports two I2C interfaces. Bootmode_I2C connects to the boot mode buffer to control the bootmode of the AM243x while the other I2C interface is connected to the I2C1 port of the AM243x.

Table 4-21 Test Automation Header Pinout
Pin # IO Direction Signal Description
1 Power VCC3V3_TA Power for test automation header
2 Power VCC3V3_TA
3 Power VCC3V3_TA
4 N/A Reserved
5 N/A Reserved
6 N/A Reserved
7 Ground DGND
8 N/A Reserved
9 N/A Reserved
10 N/A Reserved
11 N/A Reserved
12 N/A Reserved
13 N/A Reserved
14 N/A Reserved
15 N/A Reserved
16 Ground DGND
17 N/A Reserved
18 N/A Reserved
19 N/A Reserved
20 N/A Reserved
21 N/A Reserved
22 N/A Reserved
23 N/A Reserved
24 N/A Reserved
25 Ground DGND
26 Output TEST_POWERDOWN Used to power down the board
27 Output TEST_PORZn Used to reset the SoC PORz
28 Output TEST_WARMRESETn Used to reset the SoC Warm Reset
29 N/A Reserved
30 Output TA_SOC_INTn Interrupt to SoC
31 Bidirectional TEST_GPIO2
32 Output TEST_GPIO3 Used to disable the BOOTMODE buffer
33 Outpu TEST_GPIO4 Used to Reset the BOOTMODE IO Expander
34 Ground DGND
35 N/A Reserved
36 Bidirectional SOC_I2C1_TA_SCL Clock signal for SoC I2C
37 Bidirectional BOOTMODE_I2C_SCL Clock signal for I2C IO expander for boot mode
38 Bidirectional SOC_I2C1_TA_SDA Data signal for SoC I2C
39 Bidirectional BOOTMODE_I2C_SDA Data signal for I2C IO expander for boot mode
40 Ground DGND
41 Ground DGND
42 Ground DGND
Note: All pins designated as "Reserved" should be left unconnected/floating.