SPRUJ12F August 2021 – January 2024 AM2431 , AM2432 , AM2434
Power: Since the RGMII signals from the PRG1 and CPSW domain of the SoC are at 3.3 V I/O level, the Gigabit Ethernet PHY device (DP83869) is powered with I/O voltage of 3.3 V and an analog supply of 2.5 V and 1.1 V.
Clock: The 25 MHz clock is sourced from the output of the clock buffer to both Ethernet PHYs. Alternatively, RGMII2 PHY can be sourced by the OBSCLK0 output of the SoC as shown in the Clock Architecture.
Reset: The reset signal for the PHYs is driven by an AND operation between PORz_OUT and an SoC GPIO.
Interrupt: The interrupts from the two Ethernet PHYs are shorted and connect to a single GPIO of the AM243x SoC.