SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.5 Clock

All reference clocks required for the SoC and two Ethernet PHY's are generated from a single three-output clock buffer (LMK1C1103PWR), which is sourced from a single 25 MHz LVCMOS Oscillator. A single output clock buffer (SN74LV1TT34DCKR) is used to level translate from 3.3 V to 1.8 V. An optional clock is provided to RGMII2 Ethernet PHY by the OBSCLK0 output of the SoC by mounting R240 and R185 while isolating R244 and R13.

The reference clock required for XDS110 is generated locally using a 16 MHz crystal.

GUID-20210719-CA0I-QR8J-GRJD-CCCZCG1ZDB49-low.png Figure 4-6 Clock Architecture
Table 4-16 Clock Frequency Table
SI # Signal Name Reference Expected Frequency
1 SOC_CLKIN U11.4 25.000 MHz
2 SOC_CLKIN_BUFF R46 25.000 MHz
3 PRG1_CPSW_RGMII1_CLK R25 25.000 MHz
4 PRG1_CPSW_RGMII2_CLK R50 25.000 MHz
5 OSC0 Y1.3 16.000 MHz
Note: The 16 MHz clock will only become active after power is supplied to the micro-B USB connector after insertion of a cable into the micro-B USB port.