SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.7.1 Ethernet PHY Strapping

The DP83869 uses many of the functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap options are internally reloaded from the values sampled at power up or hard reset. RX_D0 and RX_D1 pins are 4-level strap pins and all other strap pins have two levels.

The Ethernet PHY includes an internal pull-down resistor. The value for the external pull resistors are selected to provide voltage at the pins of the AM243x as close to ground or 3.3 V as possible.

Address strapping is provided for the RGMII1 PHY and RGMII2 PHY to set the address to 00011 (03h) and 0111 (0Fh), respectively, using strap resistors. Footprint for both pull up and pull down is provided on all the strapping pins.

Both PHY modes are selected as RGMII to copper with auto-negotiation advertised for 1000 Base-T, 100 Base-Tx, and 10 Base-Te speeds.

The strapping configurations for both Ethernet PHYs are shown in Figure 4-11 and Figure 4-12.

GUID-20210719-CA0I-PSBS-PN13-V7MHNNH6ZWDW-low.png Figure 4-11 Ethernet PHY Strapping for RGMII1 PHY
GUID-20210719-CA0I-4MZR-0VW9-P0WDB3FGTBDL-low.png Figure 4-12 Ethernet PHY Strapping for RGMII2 PHY

Table 4-18 shows the strapping description for both Ethernet PHYs.

Table 4-18 Ethernet PHY Strapping Values
Strap Setting Pin Name Strap Function Value of Strap Function for RGMII1 Value of Strap Function for RGMII2 Description
PHY Address RX_D1 PHY_AD3 1 1 ICSSG1 PHY Address 00011
PHY_AD2 1 1
RX_D0 PHY_AD1 0 1 ICSSG2PHY Address: 01111
PHY_AD0 0 0
Modes of Operation RX_CNTL Mirror Enable 0 0 Mirror Enabled/Disabled
LED_2 ANEGSEL_1 0 0 Auto-negotiation, 10/100/1000 advertissed, Auto-MDI-X
LED_1 ANEGSEL_0 0 0
LED_0 ANEG_DIS 0 0
JTAG_TDO/GPIO_1 OPMODE_0 0 0 RGMII to Copper (1000 Base-T, 100 Base-Tx, 10 Base-Te)
RX_D2 OPMODE_1 0 0
RX_D3 OPMODE_2 0 0