Let us look more closely at the typical way in which semiconductor devices are damaged by ESD. Consider a large ESD potential, or voltage, which is applied between the inverting input and negative supply pin of an op amp (Figure 2-1).

Figure 2-1 ESD Event Voltage Path

This ESD event places a large voltage from the gate to the source of one of the input MOSFETs, which can cause damage to the device. The thickness of the MOSFET gate oxide is on the scale of nanometers, making the MOSFET very susceptible to this kind of damage.

Figure 2-2 MOSFET Diagram

ESD protection diodes provide the necessary protection to prevent this damage. Improper handling of the device can lead to inadvertent ESD events. One of the most common ways an ESD pulse can occur is through IC interaction with a human. Humans can build up an electrostatic discharge through friction against walking on a floor, brushing against furniture, etc. This charge can dissipate rapidly into an IC if touched without proper ESD protection. This is often on the scale of kilovolts, making the need for ESD cells obvious. To make sure the device can withstand these events, op amps are subjected to a quick voltage surge (in the range of kV) and tested afterwards to make sure the device is still functional. This simulation is called the human body model (HBM).

Another example of real life ESD events that is simulated in labs to make sure an IC can withstand the ESD event is the charged device model (CDM). CDM simulates events that most often occur in the manufacturing and assembly process through the build up of charge between the device and the automated test handler, or other automated devices used throughout the assembly process. When a device comes into contact with a grounded conductor, residual capacitance discharges, possibly causing damage to the IC. Careful handling of devices is required so that an ESD event is not triggered. When simulating this failure mode, devices are exposed to high voltages, then tested afterwards for functionality. Since the discharge usually takes place on the scale of nanoseconds, most failures are seen in the form of gate-oxide damage (as seen above), and junction damage.

The machine model (MM) was previously used to simulate the worst case HBM event. However, this does not accurately simulate real world ESD events, and is no longer used. Now, HBM and CDM is used to test ESD robustness in semiconductors.

JEDEC, the Joint Electron Device Engineering Council, sets the industry standards for the acceptable ESD ratings for semiconductor devices, including HBM and CDM tests. For more details on JEDEC and the industry semiconductor requirements, see the official website. All device data sheets contain the voltage threshold for the respective models. An example of a typical ESD ratings table is shown in Table 2-1, using device OPA596. Knowing the type of protection the device has is important. In the next section, the different types of ESD cells is discussed.