SWCS134A October   2017  – February 2025 TPS6508700

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (CTLx)
    13. 5.13 Digital Output Signals (IRQB, GPOx)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 SMPS Voltage Regulators
      1. 6.3.1 Controller Overview
      2. 6.3.2 Converter Overview
      3. 6.3.3 Dynamic Voltage Scaling
      4. 6.3.4 Current Limit
    4. 6.4 LDO Regulators and Load Switches
      1. 6.4.1 VTT LDO
      2. 6.4.2 LDOA1–LDOA3
      3. 6.4.3 Load Switches
    5. 6.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 6.6 Power Sequencing and Voltage-Rail Control
      1. 6.6.1 Power-Up and Power-Down Sequencing
      2. 6.6.2 Emergency Shutdown
    7. 6.7 Device Functional Modes
      1. 6.7.1 Off Mode
      2. 6.7.2 Standby Mode
      3. 6.7.3 Active Mode
    8. 6.8 I2C Interface
      1. 6.8.1 F/S-Mode Protocol
    9. 6.9 Register Maps
      1. 6.9.1  Register Map Summary
      2. 6.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 6.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 6.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 6.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 6.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 6.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 6.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 6.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 6.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 6.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 6.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 6.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 6.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 6.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 6.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 6.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 6.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 6.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 6.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 6.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 6.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 6.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 6.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 6.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 6.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 6.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 6.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 6.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 6.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 6.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 6.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = E0h]
      33. 6.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 6.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 6.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 6.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 6.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 6.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 6.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 6.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 6.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 6.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 6.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 6.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 6.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 6.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 6.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 6.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 6.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 6.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 6.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 6.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 6.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Controller With External Feedback Resistor
          2. 7.2.2.1.2 Selecting the Inductor
          3. 7.2.2.1.3 Selecting the Output Capacitors
          4. 7.2.2.1.4 Selecting the FETs
          5. 7.2.2.1.5 Bootstrap Capacitor
          6. 7.2.2.1.6 Setting the Current Limit
          7. 7.2.2.1.7 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
    3. 7.3 Power Supply Coupling and Bulk Capacitors
    4. 7.4 Dos and Don'ts
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.9 Electrical Characteristics: LDOs

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDOA1
VIN Input voltage 4.5 5 5.5 V
VOUT DC output voltage Set by LDOA1_VID[3:0] 3.3
Accuracy IOUT = 0 to 200mA –2% 2% V
IOUT DC output current 200 mA
ΔVOUT/ΔVIN Line regulation IOUT = 40mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10mA to 200mA –2% 2%
IOCP Overcurrent protection VIN = 5V, Measured with output shorted to ground 500 mA
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value,
COUT = 4.7µF		 500 µs
IQ Quiescent current IOUT = 0A 23 µA
COUT External output capacitance 2.7 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOA1_DIS[1:0] = 01b 100 Ω
LDOA1_DIS[1:0] = 10b 190 Ω
LDOA1_DIS[1:0] = 11b 450 Ω
LDOA2 and LDOA3
VIN Power input voltage VOUT + VDROP (1) 1.8 1.98 V
VOUT LDOA2 DC output voltage Set by LDOA2_VID[3:0] 1.5 V
LDOA3 DC output voltage Set by LDOA3_VID[3:0] 1.2 V
DC output voltage accuracy IOUT = 0 to 600mA –2% 3%
IOUT DC output current 600 mA
VDROP Dropout voltage VOUT = 0.99 × VOUT_NOM,
IOUT = 600mA		 350 mV
ΔVOUT/ΔVIN Line regulation IOUT = 300mA –0.5% 0.5%
ΔVOUT/ΔIOUT Load regulation IOUT = 10mA to 600mA –2% 2%
IOCP Overcurrent protection Measured with output shorted to ground 0.65 1.25 A
VTH_PG Power good assertion threshold in percentage of target VOUT VOUT rising 108%
VOUT falling 92%
tSTARTUP Start-up time Measured from EN = H to reach 95% of final value, COUT = 4.7µF 500 µs
IQ Quiescent current IOUT = 0A 20 µA
LDOA2 and LDOA3 (continued)
PSRR Power supply rejection ratio f = 1kHz, VIN = 1.8V, VOUT = 1.2V,
IOUT = 300mA,
COUT = 2.2µF – 4.7µF		 48 dB
f = 10kHz, VIN = 1.8 V, VOUT = 1.2V,
IOUT = 300mA,
COUT = 2.2µF – 4.7µF		 30 dB
COUT External output capacitance 2.2 4.7 10 µF
ESR 100 mΩ
RDIS Output auto-discharge resistance LDOAx_DIS[1:0] = 01b 80 Ω
LDOAx_DIS[1:0] = 10b 180
LDOAx_DIS[1:0] = 11b 475
VTT LDO
VIN Power input voltage 1.2 3.3 V
VOUT DC output voltage VIN = 1.2V, Measured at VTTFB pin VIN / 2 V
DC output voltage accuracy Relative to VIN / 2, IOUT ≤ 10mA,
1.1V ≤ VIN ≤ 1.35V		 –10 10 mV
Relative to VIN / 2, IOUT ≤ 500mA,
1.1V ≤ VIN ≤ 1.35V		 –25 25
IOUT DC output current sink(–) and source(+) –500 500 mA
ΔVOUT/ΔIOUT Load regulation 1.1 V ≤ VIN ≤ 1.35V,
IOUT = –500mA to 500mA		 –4% 4%
IOCP Overcurrent protection Measured with output shorted to ground 0.95 A
VTH_PG Power good deassertion threshold in percentage of target VOUT VOUT rising 110%
VOUT falling 95%
VTH_HYS_PG Power good reassertion hysteresis entering back into VTH_PG 5%
IQ Total ground current VIN = 1.2V, IOUT = 0A 240 µA
ILKG OFF leakage current VIN = 1.2V, disabled 1 µA
CIN External input capacitance 10 µF
COUT External output capacitance 35 µF
RDIS Output auto-discharge resistance VTT_DIS = 0b 1000 kΩ
VTT_DIS = 1b 60 80 100 Ω
(1) It must be equal to or greater than 1.62V.