SWCS134A October   2017  – February 2025 TPS6508700

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (CTLx)
    13. 5.13 Digital Output Signals (IRQB, GPOx)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 SMPS Voltage Regulators
      1. 6.3.1 Controller Overview
      2. 6.3.2 Converter Overview
      3. 6.3.3 Dynamic Voltage Scaling
      4. 6.3.4 Current Limit
    4. 6.4 LDO Regulators and Load Switches
      1. 6.4.1 VTT LDO
      2. 6.4.2 LDOA1–LDOA3
      3. 6.4.3 Load Switches
    5. 6.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 6.6 Power Sequencing and Voltage-Rail Control
      1. 6.6.1 Power-Up and Power-Down Sequencing
      2. 6.6.2 Emergency Shutdown
    7. 6.7 Device Functional Modes
      1. 6.7.1 Off Mode
      2. 6.7.2 Standby Mode
      3. 6.7.3 Active Mode
    8. 6.8 I2C Interface
      1. 6.8.1 F/S-Mode Protocol
    9. 6.9 Register Maps
      1. 6.9.1  Register Map Summary
      2. 6.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 6.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 6.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 6.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 6.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 6.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 6.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 6.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 6.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 6.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 6.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 6.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 6.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 6.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 6.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 6.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 6.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 6.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 6.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 6.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 6.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 6.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 6.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 6.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 6.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 6.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 6.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 6.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 6.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 6.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 6.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = E0h]
      33. 6.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 6.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 6.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 6.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 6.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 6.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 6.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 6.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 6.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 6.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 6.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 6.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 6.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 6.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 6.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 6.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 6.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 6.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 6.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 6.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 6.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Controller With External Feedback Resistor
          2. 7.2.2.1.2 Selecting the Inductor
          3. 7.2.2.1.3 Selecting the Output Capacitors
          4. 7.2.2.1.4 Selecting the FETs
          5. 7.2.2.1.5 Bootstrap Capacitor
          6. 7.2.2.1.6 Setting the Current Limit
          7. 7.2.2.1.7 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
    3. 7.3 Power Supply Coupling and Bulk Capacitors
    4. 7.4 Dos and Don'ts
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.8.1 F/S-Mode Protocol

The master initiates a data transfer by generating a start condition. The start condition is a high-to-low transition that occurs on the SDA line while SCL is high (see Figure 6-9). All I2C-compatible devices should recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read-write direction bit, R/W, on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 6-10). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 6-11) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master identifies that the communication link with a slave has been established.

The master generates additional SCL cycles to either transmit data to the slave (R/W bit is 0b) or receive data from the slave (R/W bit is 1b). In either case, the receiver must acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as required.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 6-9). This process releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon receiving a stop condition, all devices identify that the bus is released, and wait for a start condition followed by a matching address.

TPS6508700 START and STOP ConditionsFigure 6-9 START and STOP Conditions
TPS6508700 Bit Transfer on the I2C BusFigure 6-10 Bit Transfer on the I2C Bus
TPS6508700 Acknowledge on the I2C BusFigure 6-11 Acknowledge on the I2C Bus
TPS6508700 I2C Bus ProtocolFigure 6-12 I2C Bus Protocol
TPS6508700 I2C Interface WRITE to TPS6508700 in F/S ModeFigure 6-13 I2C Interface WRITE to TPS6508700 in F/S Mode
TPS6508700 I2C Interface READ From TPS6508700 in F/S Mode (Only Repeated START is Supported)Figure 6-14 I2C Interface READ From TPS6508700 in F/S Mode (Only Repeated START is Supported)