SWCS134A October   2017  – February 2025 TPS6508700

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Total Current Consumption
    6. 5.6  Electrical Characteristics: Reference and Monitoring System
    7. 5.7  Electrical Characteristics: Buck Controllers
    8. 5.8  Electrical Characteristics: Synchronous Buck Converters
    9. 5.9  Electrical Characteristics: LDOs
    10. 5.10 Electrical Characteristics: Load Switches
    11. 5.11 Digital Signals: I2C Interface
    12. 5.12 Digital Input Signals (CTLx)
    13. 5.13 Digital Output Signals (IRQB, GPOx)
    14. 5.14 Timing Requirements
    15. 5.15 Switching Characteristics
    16. 5.16 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 SMPS Voltage Regulators
      1. 6.3.1 Controller Overview
      2. 6.3.2 Converter Overview
      3. 6.3.3 Dynamic Voltage Scaling
      4. 6.3.4 Current Limit
    4. 6.4 LDO Regulators and Load Switches
      1. 6.4.1 VTT LDO
      2. 6.4.2 LDOA1–LDOA3
      3. 6.4.3 Load Switches
    5. 6.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 6.6 Power Sequencing and Voltage-Rail Control
      1. 6.6.1 Power-Up and Power-Down Sequencing
      2. 6.6.2 Emergency Shutdown
    7. 6.7 Device Functional Modes
      1. 6.7.1 Off Mode
      2. 6.7.2 Standby Mode
      3. 6.7.3 Active Mode
    8. 6.8 I2C Interface
      1. 6.8.1 F/S-Mode Protocol
    9. 6.9 Register Maps
      1. 6.9.1  Register Map Summary
      2. 6.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 6.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 6.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 6.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 6.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 6.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 6.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 6.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 6.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 6.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 6.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 6.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 6.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 6.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 6.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 6.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 6.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 6.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 6.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 6.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 6.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 6.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 6.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 6.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 6.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 6.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 6.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 6.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 6.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 6.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 6.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = E0h]
      33. 6.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 6.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 6.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 6.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 6.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 6.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 6.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 6.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 6.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 6.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 6.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 6.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 6.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 6.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 6.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 6.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 6.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 6.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 6.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 6.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 6.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Controller Design Procedure
          1. 7.2.2.1.1 Controller With External Feedback Resistor
          2. 7.2.2.1.2 Selecting the Inductor
          3. 7.2.2.1.3 Selecting the Output Capacitors
          4. 7.2.2.1.4 Selecting the FETs
          5. 7.2.2.1.5 Bootstrap Capacitor
          6. 7.2.2.1.6 Setting the Current Limit
          7. 7.2.2.1.7 Selecting the Input Capacitors
        2. 7.2.2.2 Converter Design Procedure
          1. 7.2.2.2.1 Selecting the Inductor
          2. 7.2.2.2.2 Selecting the Output Capacitors
          3. 7.2.2.2.3 Selecting the Input Capacitors
        3. 7.2.2.3 LDO Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout
        1. 7.2.4.1 Layout Guidelines
        2. 7.2.4.2 Layout Example
    3. 7.3 Power Supply Coupling and Bulk Capacitors
    4. 7.4 Dos and Don'ts
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with a programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include an integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow the use of inductors in a small form factor, reducing total-system cost and size.

BUCK1–BUCK6 have selectable auto-PWM and forced-PWM mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto-PWM mode, the VR automatically switches between pulse width modulation (PWM) and pulse frequency modulation (PFM) depending on the output load to maximize efficiency.

All controllers and converters can be set to the default output voltage (VOUT) or dynamically voltage changing at any time. This feature means that the rails can be programmed for any VOUT by the factory, therefore the device starts up with the default voltage, or during operation the rail can be programmed to another operating VOUT while the rail is enable or disabled. Two step sizes, or ranges, are available for VOUT selection: 10-mV steps and 25-mV steps. The step-size range must be selected prior to use and must be programmed by the factory. The step-size range is not subject to programming or change during operation.

Table 6-2 lists the options for the 10-mV step-size range VOUT. Table 6-3 lists the options for the 25-mV step-size range VOUT.

Table 6-2 10-mV Step-Size VOUT Range
VID BITS VOUT VID BITS VOUT VID BITS VOUT
0000000b 0 0101011b 0.83 1010110b 1.26
0000001b 0.41 0101100b 0.84 1010111b 1.27
0000010b 0.42 0101101b 0.85 1011000b 1.28
0000011b 0.43 0101110b 0.86 1011001b 1.29
0000100b 0.44 0101111b 0.87 1011010b 1.30
0000101b 0.45 0110000b 0.88 1011011b 1.31
0000110b 0.46 0110001b 0.89 1011100b 1.32
0000111b 0.47 0110010b 0.90 1011101b 1.33
0001000b 0.48 0110011b 0.91 1011110b 1.34
0001001b 0.49 0110100b 0.92 1011111b 1.35
0001010b 0.50 0110101b 0.93 1100000b 1.36
0001011b 0.51 0110110b 0.94 1100001b 1.37
0001100b 0.52 0110111b 0.95 1100010b 1.38
0001101b 0.53 0111000b 0.96 1100011b 1.39
0001110b 0.54 0111001b 0.97 1100100b 1.40
0001111b 0.55 0111010b 0.98 1100101b 1.41
0010000b 0.56 0111011b 0.99 1100110b 1.42
0010001b 0.57 0111100b 1.00 1100111b 1.43
0010010b 0.58 0111101b 1.01 1101000b 1.44
0010011b 0.59 0111110b 1.02 1101001b 1.45
0010100b 0.60 0111111b 1.03 1101010b 1.46
0010101b 0.61 1000000b 1.04 1101011b 1.47
0010110b 0.62 1000001b 1.05 1101100b 1.48
0010111b 0.63 1000010b 1.06 1101101b 1.49
0011000b 0.64 1000011b 1.07 1101110b 1.50
0011001b 0.65 1000100b 1.08 1101111b 1.51
0011010b 0.66 1000101b 1.09 1110000b 1.52
0011011b 0.67 1000110b 1.10 1110001b 1.53
0011100b 0.68 1000111b 1.11 1110010b 1.54
0011101b 0.69 1001000b 1.12 1110011b 1.55
0011110b 0.70 1001001b 1.13 1110100b 1.56
0011111b 0.71 1001010b 1.14 1110101b 1.57
0100000b 0.72 1001011b 1.15 1110110b 1.58
0100001b 0.73 1001100b 1.16 1110111b 1.59
0100010b 0.74 1001101b 1.17 1111000b 1.60
0100011b 0.75 1001110b 1.18 1111001b 1.61
0100100b 0.76 1001111b 1.19 1111010b 1.62
0100101b 0.77 1010000b 1.20 1111011b 1.63
0100110b 0.78 1010001b 1.21 1111100b 1.64
0100111b 0.79 1010010b 1.22 1111101b 1.65
0101000b 0.80 1010011b 1.23 1111110b 1.66
0101001b 0.81 1010100b 1.24 1111111b 1.67
0101010b 0.82 1010101b 1.25 — —
Table 6-3 25-mV Step-Size VOUT Range
VID BITS VOUT (Converters) VOUT (Controllers) VID BITS VOUT VID BITS VOUT
0000000b 0 1.000 0101011b 1.475 1010110b 2.550
0000001b 0.425 1.000 0101100b 1.500 1010111b 2.575
0000010b 0.450 1.000 0101101b 1.525 1011000b 2.600
0000011b 0.475 1.000 0101110b 1.550 1011001b 2.625
0000100b 0.500 1.000 0101111b 1.575 1011010b 2.650
0000101b 0.525 1.000 0110000b 1.600 1011011b 2.675
0000110b 0.550 1.000 0110001b 1.625 1011100b 2.700
0000111b 0.575 1.000 0110010b 1.650 1011101b 2.725
0001000b 0.600 1.000 0110011b 1.675 1011110b 2.750
0001001b 0.625 1.000 0110100b 1.700 1011111b 2.775
0001010b 0.650 1.000 0110101b 1.725 1100000b 2.800
0001011b 0.675 1.000 0110110b 1.750 1100001b 2.825
0001100b 0.700 1.000 0110111b 1.775 1100010b 2.850
0001101b 0.725 1.000 0111000b 1.800 1100011b 2.875
0001110b 0.750 1.000 0111001b 1.825 1100100b 2.900
0001111b 0.775 1.000 0111010b 1.850 1100101b 2.925
0010000b 0.800 1.000 0111011b 1.875 1100110b 2.950
0010001b 0.825 1.000 0111100b 1.900 1100111b 2.975
0010010b 0.850 1.000 0111101b 1.925 1101000b 3.000
0010011b 0.875 1.000 0111110b 1.950 1101001b 3.025
0010100b 0.900 1.000 0111111b 1.975 1101010b 3.050
0010101b 0.925 1.000 1000000b 2.000 1101011b 3.075
0010110b 0.950 1.000 1000001b 2.025 1101100b 3.100
0010111b 0.975 1.000 1000010b 2.050 1101101b 3.125
0011000b 1.000 1.000 1000011b 2.075 1101110b 3.150
0011001b 1.025 1.025 1000100b 2.100 1101111b 3.175
0011010b 1.050 1.050 1000101b 2.125 1110000b 3.200
0011011b 1.075 1.075 1000110b 2.150 1110001b 3.225
0011100b 1.100 1.100 1000111b 2.175 1110010b 3.250
0011101b 1.125 1.125 1001000b 2.200 1110011b 3.275
0011110b 1.150 1.150 1001001b 2.225 1110100b 3.300
0011111b 1.175 1.175 1001010b 2.250 1110101b 3.325
0100000b 1.200 1.200 1001011b 2.275 1110110b 3.350
0100001b 1.225 1.225 1001100b 2.300 1110111b 3.375
0100010b 1.250 1.250 1001101b 2.325 1111000b 3.400
0100011b 1.275 1.275 1001110b 2.350 1111001b 3.425
0100100b 1.300 1.300 1001111b 2.375 1111010b 3.450
0100101b 1.325 1.325 1010000b 2.400 1111011b 3.475
0100110b 1.350 1.350 1010001b 2.425 1111100b 3.500
0100111b 1.375 1.375 1010010b 2.450 1111101b 3.525
0101000b 1.400 1.400 1010011b 2.475 1111110b 3.550
0101001b 1.425 1.425 1010100b 2.500 1111111b 3.575
0101010b 1.450 1.450 1010101b 2.525 — —