TIDUDS9B December   2017  – November 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Conditions of Use: Assumption
        1. 2.2.1.1 Generic Assumptions
        2. 2.2.1.2 Specific Assumptions
      2. 2.2.2 Diagnostics Coverage
        1. 2.2.2.1 Dual-Channel Monitoring
        2. 2.2.2.2 Checking ISO1211 Functionality With MCU (SIL1)
        3. 2.2.2.3 Checking TPS22919 Functionality With MCU (SIL1)
        4. 2.2.2.4 Checking TPS27S100 Functionality With MCU (SIL1)
        5. 2.2.2.5 Optional Monitoring Using RDY Pin of ISO5452, ISO5852S or UCC21750 Integrated Analog-to-PWM Isolated Sensor
      3. 2.2.3 Drive State
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO1211
      2. 2.3.2 TPS27S100
      3. 2.3.3 TPS22919
      4. 2.3.4 ISO5852S, ISO5452
    4. 2.4 System Design Theory
      1. 2.4.1 Digital Input Receiver for STO
      2. 2.4.2 STO_1 Signal Flow Path for Controlling VCC1
      3. 2.4.3 STO_2 Signal Flow Path
        1. 2.4.3.1 High-Side Switch for Controlling Secondary-Side Supply Voltage of Gate Driver
        2. 2.4.3.2 Powering up Secondary Side: VCC2 of Gate Driver
      4. 2.4.4 Gate Driver Design
      5. 2.4.5 STO_FB Signal Flow Path
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 PCB Overview
    2. 3.2 Testing and Results
      1. 3.2.1 Logic High and Logic Low STO Thresholds
      2. 3.2.2 Validation of STO1 Signal
        1. 3.2.2.1 Propagation of STO1 to VCC1 of Gate Driver
        2. 3.2.2.2 1-ms STO Pulse Rejection
        3. 3.2.2.3 Diagnostic Pulses From MCU Interface
      3. 3.2.3 Validation of STO2 Signals
        1. 3.2.3.1 Propagation of STO2 to VCC2 of Gate Driver
        2. 3.2.3.2 1-ms Pulse Rejection
        3. 3.2.3.3 Diagnostic Pulses From MCU
        4. 3.2.3.4 Inrush Current Measurement
      4. 3.2.4 3.3-V Voltage Rail From Switcher
      5. 3.2.5 60-V Input Voltage and Reverse Polarity Protection
      6. 3.2.6 Validation of Trip Zone Functionality
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Layer Plots
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
    1. 5.1 Trademarks
  11. 6About the Author
  12. 7Recognition
  13. 8Revision History

2.4.1 Digital Input Receiver for STO

The ISO1211 receives 24-V digital signals and provides isolated digital outputs, without the requirement of a field-side power supply. External resists on the input signal path (R12 and R21) precisely set the limit for the current drawn from the field input. This current limit helps to minimize the power dissipated in the system. The current limit can be set for Type 1, 2, or 3 operation. The voltage transition thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external resistor, R22 and R15. These two resistors are carbon MELF (pulse-proof) type used to prevent surge. For detailed test results, see the How to Design Isolated Digital Input Modules for Surge Immunity application brief.

Figure 2-10 shows a schematic of the ISO1211 receivers.

GUID-20220307-SS0I-CH7G-R4XQ-0XCGL1KKPZWW-low.png Figure 2-10 ISO1211 Schematic

As per the specifications of the design, the voltage limits defined for an input voltage of 24 V is as follows:

  1. 15- to 30-V DC: STO function not engaged (motion allowed)
  2. 0- to 5-V DC: STO function engaged (motion inhibited)

These design requirements comply with Type 1 characteristics.

As Figure 2-10 shows, Type 1 operation uses a value of 560 Ω for R12 and R21 and results in a current limit of 2.25 mA (typical). The relationship between the RSENSE resistor and the typical current limit (IL) is given by Equation 1.

Equation 1. GUID-DBA80E7D-28F2-4C6F-AB49-00FCDBB03503-low.gif

Resistors R22 and R15 set the voltage thresholds (VIH and VIL) in addition to limiting the surge current. Use a resistor of 2.5 kΩ for R22 and R15 for a Type 1 system. Equation 2 and Equation 3 are used to calculate the typical VIH and VIL values, respectively.

Equation 2. VIH(TYPICAL)=8.25 V+R22×2.25 mA×562 ΩR21=8.25 V+2.5 kΩ×2.25 mA×562 Ω560 Ω=13.875 V
Equation 3. VIL(TYPICAL)=7.1 V+R22×2.25 mA×562 ΩR21=7.1 V+2.5 kΩ×2.25 mA×562 Ω560 Ω=12.725 V

Note that the specific assumption of input signals STO_1 and STO_2 is that the input voltage is between 0-V and 24-V nominal with worst case of 3.6-V as logic low and 20.4-V as logic high. Logic high range is 24-V DC ±15% (nominal) with ±60-V DC absolute maximum. No intermediate voltage is expected.

As per the design specifications, low STO pulses that are less than 1 ms are rejected. Address this rejection by placing a low-pass filter at the output signals of the ISO1211 device. To meet the design requirements, place an RC combination with R = 1 k and C = 3.3 μF (see Equation 4).

Equation 4. GUID-CB090E61-34EC-4423-8DC9-12E7E60A6654-low.gif

The cutoff frequency of this filter is 48 Hz, where:

  • V(t) = 3.3
  • At t = 1 ms
  • V(t) = 2.8 V, which is within the logic threshold high range of the AND gate.

For implementation, use 2 × 499 Ω R17 and R20 in series for STO 1 and use 2 × 499 Ω R6 and R13 in series for STO 2. This is to get rid of the short or change value failure mode of resistor which will bypass the filter for logic gate input.