TIDUE74F April   2018  – March 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000™ Real-Time MCU LaunchPad™ Development Kit
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 Tamagawa T-Format Protocol
      2. 2.3.2 C2000 T-Format Encoder Interface Overview
      3. 2.3.3 TIDM-1011 Board Implementation
      4. 2.3.4 MCU Resource Requirements
      5. 2.3.5 Device-Specific Resource Usage
        1. 2.3.5.1 CRC Calculations
        2. 2.3.5.2 Input, Output Signals, and CLB Tiles
      6. 2.3.6 CLB T-Format Implementation Details
        1. 2.3.6.1 Transaction Waveforms
          1. 2.3.6.1.1 IDLE State
          2. 2.3.6.1.2 TRANSMIT_DATA State
          3. 2.3.6.1.3 WAIT_FOR_START State
          4. 2.3.6.1.4 RECEIVE_DATA State
        2. 2.3.6.2 Communication Tile Design
        3. 2.3.6.3 Logic View
      7. 2.3.7 CLB Receive Data CRC Implementation
      8. 2.3.8 PM T-Format Encoder Interface Library
        1. 2.3.8.1 PM T-Format Reference Implementation Commands
        2. 2.3.8.2 Functions Supported in PM T-Format Reference Implementation
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1011 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Code
      4. 3.3.4 Cable Length Validation
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Related Documentation
    1. 5.1 Trademarks
  12. 6Terminology
  13. 7About the Authors
  14. 8Revision History

2.3.6.1 Transaction Waveforms

When implementing a CLB design, first visualizing the required CLB behavior using waveforms can be helpful. To do this, first consider an an example transaction. Recall a T-Format transaction consists of the request transmission plus the encoder's response. A transmission can be broken up into FRAME_STATEs as shown in Figure 2-12. The first step is to map each element of the transaction to a CLB submodule. Table 2-12 shows an example mapping.

Table 2-12 T-Format Transaction to CLB Mapping
Transaction Behavior CLB Mapping
Track the FRAME_STATE Finite State Machine (FSM): transitions to a new state given the previous state and current inputs.
Count the clocks generated A COUNTER: configured to increment a clock edge during the TRANSMIT_DATA and RECEIVE_DATA states. The mode0 input controls when the counter is active and when the counter is halted. Leverage the COUNTER's match values to drive state transitions (TRANSMIT_DATA to WAIT_FOR_START and RECEIVE_DATA to IDLE).
Generate a clock signal of a specific width This requirement maps to a second COUNTER. Leverage the match values to generate the timing for the the rising/falling edges. A LUT (Lookup Table) then generates the actual edges based on this timing.
Align the clock with the encoder's response The COUNTER generating the clock can be configured such that the edge transition is properly aligned with the encoder's response.
Only allow the SPI to be clocked during transmit and receive A LUT blocks the clock when not needed.
Control the TxEN A LUT leverages the current FRAME_STATE to control the signal.
Tell the CLB to start the transaction The C28x configures the COUNTER and SPI for the transaction. The CLB GPREG allows the C28x CPU to directly change a CLB input to start a transaction.
TIDM-1011 T-Format Transaction Example Figure 2-12 T-Format Transaction Example

The next step is visualization of the specific submodule behavior. Start with a quick sketch and then add additional detail as the design develops. Figure 2-13 shows an example waveform.

TIDM-1011 CLB Communication Waveform Figure 2-13 CLB Communication Waveform
Note: Figure 2-13 was generated using the CLB SystemC simulation model with a custom input as the encoder's response. The transmitted request is not specifically shown in Figure 2-13. The SPI module sends the request based on the CLB_SPI_CLK during the TRANSMIT_DATA (or SEND_DATA) phase.

Markers 1 - 6 in Figure 2-13 are used in the following sections to describe specific behavior of the design with respect to that marker. The markers are:

  1. Transition from IDLE to TRANSMIT_DATA (or SEND_DATA)
  2. Transition to WAIT_FOR_START
  3. During WAIT_FOR_START
  4. Transition to RECEIVE_DATA
  5. During RECEIVE_DATA
  6. Transition back to IDLE

Following the description of each FRAME_STATE, Section 2.3.6.2 presents the complete tile design. Refer to Section 2.3.6.2 along with Figure 2-13while reading the descriptions of each state.