TIDUE74F April   2018  – March 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000™ Real-Time MCU LaunchPad™ Development Kit
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 Tamagawa T-Format Protocol
      2. 2.3.2 C2000 T-Format Encoder Interface Overview
      3. 2.3.3 TIDM-1011 Board Implementation
      4. 2.3.4 MCU Resource Requirements
      5. 2.3.5 Device-Specific Resource Usage
        1. 2.3.5.1 CRC Calculations
        2. 2.3.5.2 Input, Output Signals, and CLB Tiles
      6. 2.3.6 CLB T-Format Implementation Details
        1. 2.3.6.1 Transaction Waveforms
          1. 2.3.6.1.1 IDLE State
          2. 2.3.6.1.2 TRANSMIT_DATA State
          3. 2.3.6.1.3 WAIT_FOR_START State
          4. 2.3.6.1.4 RECEIVE_DATA State
        2. 2.3.6.2 Communication Tile Design
        3. 2.3.6.3 Logic View
      7. 2.3.7 CLB Receive Data CRC Implementation
      8. 2.3.8 PM T-Format Encoder Interface Library
        1. 2.3.8.1 PM T-Format Reference Implementation Commands
        2. 2.3.8.2 Functions Supported in PM T-Format Reference Implementation
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1011 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Code
      4. 3.3.4 Cable Length Validation
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Related Documentation
    1. 5.1 Trademarks
  12. 6Terminology
  13. 7About the Authors
  14. 8Revision History

2.3.6.2 Communication Tile Design

TIDM-1011 T-Format Communication Tile Figure 2-14 T-Format Communication Tile

The communication tile design is shown in Figure 2-14. This section discusses in depth three key components of the design:

  1. FRAME_STATE generation (FSM_1)
  2. ENCODER_RESPONSE detection (LUT_1)
  3. SPI CLK alignment (LUT_0)
Note: In Figure 2-14, a letter in a colored circle indicates an off-page connection described in the input/output diagrams (Section 2.3.5.2).

The equations for other submodules can be found by reviewing the tile's configuration in the CLB tool. Section 2.3.6.3 includes additional information in the form of a schematic for each block.

The FRAME_STATE (FSM_1 s1, s0) transitions are shown in Figure 2-14. To derive the corresponding equations Karnaugh maps are used (Table 2-13 and Table 2-14). The resulting equations are combined by an OR operator and entered into the CLB tool. The equations do not need to be reduced to their simplest form.

Table 2-13 FRAME_STATE FSM_1 Karnaugh Map, State s0
Current Input
(e1, e0)
CLOCK_COMPLETE, TX_OR_RX
0,0 0,1 1,1 1,0
Previous State
s1, s0		 0,0
IDLE		 0
IDLE		 1(1)
TX		 1(1)
TX		 0
IDLE
0,1
TX		 1(2)
TX		 1(2)
TX		 0
WAIT		 0
WAIT
1,1
RX		 1(3)
RX		 1(3)
RX		 0
IDLE		 0
IDLE
1,0
WAIT		 0
WAIT		 1(4)
RX		 1(4)
RX		 0
WAIT
(1) s0 = (!s1 & !s0 & e0)
(2) s0 = (!s1 & s0 & !e1)
(3) s0 = (s1 & s0 & !e1)
(4) s0 = (s1 & !s0 & e0)
Table 2-14 FRAME_STATE FSM_1 Karnaugh Map, State s1
Current Input
(e1, e0)
CLOCK_COMPLETE, TX_OR_RX
0,0 0,1 1,1 1,0
Previous State
s1, s0		 0,0
IDLE		 0
IDLE		 0
TX		 0
TX		 0
IDLE
0,1
TX		 0
TX		 0
TX		 1(1)
WAIT		 1(1)
WAIT
1,1
RX		 1(2)
RX		 1(2)
RX		 0
IDLE		 0
IDLE
1,0
WAIT		 1(3)
WAIT		 1(3)
RX		 1(3)
RX		 1(3)
WAIT
(1) s1 = (!s1 & s0 & e1)
(2) s1 = (s1 & s0 & !e1)
(3) s1 = (s1 & !s0)

The OUT signal from FSM_1 is simply an OR of the current states: s1 | s2. This corresponds to any active portion of the frame (not IDLE).

Detection of the encoder's response is another a key component of the design. LUT_1 is responsible for detecting the start of the transaction and the start of the encoder's response. To simplify the design, the following assumptions have been made:

  • ENCODER_RESPONSE falling edge never occurs at the same time as START_OPERATION rising edge.
  • The START_OPERATION's rising edge only occurs during the IDLE state.

These assumptions are reasonable given the encoder only responds to a transmission initiated from the C28x and the C28x controls START_OPERATION. These assumptions result in the equation: out = (i3 & i2) & i1 | i0:

  • If FRAME_STATE == WAIT_FOR_START (i3 & i2) and ENCODER_RESPONSE falling edge (i1) then output goes high.
  • If START_OPERATION rising edge (i0), then the output goes high
  • Otherwise the output is low.

The encoder's response can come at any time due to cable delays. To to read the response correctly, the CLB_SPI_CLK must be correctly aligned. LUT_0 is responsible for both the clock alignment and the width of the clock. Both alignment and clock width are achieved by LUT_0 resetting COUNTER_0 at the appropriate time. COUNTER_0 match values control the CLB_SPI_CLOCK edge timing.

  • Clock width: reset COUNTER_0 when CLOCK_WIDTH_REACHED (i3) is high.
  • Align the clock: If the FRAME_STATE is WAIT_FOR_START (i2 & !i1) or RECEIVE_DATA (i2 & i1), then reset COUNTER_0 on ENCODER_RESPONSE any edge (i0).

This results in the equation: LUT_0 out = i3 | ( ( ( i2 & !i1) | (i2 & i1) ) & i0 ).

The equations for other submodules can be examined by reviewing the tile's configuration in the CLB tool. Section 2.3.6.3 includes additional information in the form of a schematic for each block.