TIDUE74F April   2018  – March 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000™ Real-Time MCU LaunchPad™ Development Kit
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 Tamagawa T-Format Protocol
      2. 2.3.2 C2000 T-Format Encoder Interface Overview
      3. 2.3.3 TIDM-1011 Board Implementation
      4. 2.3.4 MCU Resource Requirements
      5. 2.3.5 Device-Specific Resource Usage
        1. 2.3.5.1 CRC Calculations
        2. 2.3.5.2 Input, Output Signals, and CLB Tiles
      6. 2.3.6 CLB T-Format Implementation Details
        1. 2.3.6.1 Transaction Waveforms
          1. 2.3.6.1.1 IDLE State
          2. 2.3.6.1.2 TRANSMIT_DATA State
          3. 2.3.6.1.3 WAIT_FOR_START State
          4. 2.3.6.1.4 RECEIVE_DATA State
        2. 2.3.6.2 Communication Tile Design
        3. 2.3.6.3 Logic View
      7. 2.3.7 CLB Receive Data CRC Implementation
      8. 2.3.8 PM T-Format Encoder Interface Library
        1. 2.3.8.1 PM T-Format Reference Implementation Commands
        2. 2.3.8.2 Functions Supported in PM T-Format Reference Implementation
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1011 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Code
      4. 3.3.4 Cable Length Validation
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Related Documentation
    1. 5.1 Trademarks
  12. 6Terminology
  13. 7About the Authors
  14. 8Revision History

2.3.7 CLB Receive Data CRC Implementation

As explained in Section 2.3.5.1, CLB type 2 or later has the capability of calculating the response-data CRC as the response is being received, or on-the-fly. In this case, required signals are connected to a second tile to perform the CRC calculation. The connections between tiles are documented in Section 2.3.5.2.

To generate a CRC, a counter is configured as a Linear Feedback Shift Register (LFSR). Data received is fed to the event input of the LFSR. When data is valid, a shift is applied through the LFSR's event input. This design requires knowing when the data is valid so the shift can be properly applied. Recalling the protocol overview in Section 2.3.1, the criteria for valid data is:

  • FRAME_STATE is RECEIVE_DATA
  • The current bit is one of the 8-bits of data within the field. That is, the start and delimiter are skipped. This is visualized in Figure 2-22.
  • The field is not the CRCField. The CRC is always the last field in the encoder's response.
TIDM-1011 CRC Field Data Valid Figure 2-21 CRC Field Data Valid

The specific requirements map to CLB functionality as shown in Table 2-15.

Table 2-15 CRC Generation to CLB Mapping
CRC Functionality CLB Mapping
Include only 8-bits of data (skip start and delimiter) COUNTER module to count the bits within a T-Format field. The match values indicate the first valid bit, and the last valid bit as shown in Figure 2-21. An FSM then determines if the shift is applied to the LFSR based on the counter match outputs.
Include only valid fields (skip the CRC). COUNTER module that increments at the start of each field during the RECEIVE_DATA state. When the CRCField is reached, the match output is asserted.
Control the shift (mode0) of the LFSR Use a LUT to determine if the data is valid based on the bit count, and field count. If valid, the LUT applies a shift pulse to the LFSR.

Figure 2-22 shows an example waveform for Data ID3 CRC generation. Figure 2-23 shows the CRC tile implementation. The equations for the submodules can be viewed using the CLB Tool.

TIDM-1011 CRC Waveform Data ID3 Figure 2-22 CRC Waveform Data ID3
TIDM-1011 CLB Receive Data CRC Generation Tile Figure 2-23 CLB Receive Data CRC Generation Tile