TIDUDS9B December 2017 – November 2022
This reference design outlines a safe torque off (STO) subsystem for a 3-phase inverter with CMOS input isolated IGBT gate drivers. The STO subsystem employs a dual channel architecture (1oo2) with a hardware fault tolerance of 1 (HFT=1). It is implemented following a de-energize trip concept. When the dual STO inputs (STO_1 and STO_2) go active low, the corresponding power supplies of the primary and the secondary side of the six isolated IGBT gate drivers are cut off through load switches, hence removing the possibility to control and energize the motor. The STO reference design (1oo2) has been assessed by the TUEV SUED to be generally suitable for SIL 3 and PL e | Cat. 3.