Packaging information
| Package | Pins FCBGA (ABJ) | 400 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 90 | JEDEC TRAY (5+1) |
Features for the AFE7900
- Request full data sheet
- Quad RF sampling 12-GSPS transmit DACs
- Quad RF sampling 3-GSPS receive ADCs
- Dual RF sampling 3-GSPS feedback (auxilliary RX) ADCs
- Maximum RF signal bandwidth:
- 4TX or 2FB: 1200 MHz or 2TX: 2400 MHz
- RX): 1200 MHz (no FB), 600 MHz (with FB)
- RF frequency range:
- TX: 5MHz - 7.4GHz
- RX/FB: 5MHz - 7.4GHz
- Digital step attenuators (DSA):
- TX: 40 dB range, 0.125-dB steps
- RX or FB: 25 dB range, 0.5-dB steps
- Single or dual-band DUC or DDCs for TX and RX
- 16x NCOs per TX or RX and FB
- Optional Internal PLL or VCO for DAC or ADC clocks or external clock at DAC or ADC sample rate
- Sysref Alignment Detector
- SerDes data interface:
- JESD204B and JESD204C compatible
- 8 SerDes transceivers up to 29.5 Gbps
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
Description for the AFE7900
The AFE7900 is a high performance, wide bandwidth multi-channel transceiver, integrating four RF sampling transmitter chains, four RF sampling receiver chains and two RF sampling feedback chains (six RF sampling ADCs total). With operation up to 7.4 GHz, this device enables direct RF sampling in the L, S and C-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
The TX signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth for four TX or 2400 MHz for two TX. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.