Receivers

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

The ADC32RF80 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF80 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

The LM15851EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ LM15851. The LM15851 is a wideband sampling and digital tuning device with a buffered analog input, integrated Digital Down Converter with programmable NCO and Decimation settings and features a (...)