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Product details

Parameters

Function Counter Bits (#) 7 Technology Family CD4000 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Separate clock-up and clock-down lines
  • Capable of driving common cathode LEDs and other displays directly
  • Allows cascading without any external circuitry
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    1 V at VDD = 5 V
    2 V at VDD = 10 V
    2.5 V at VDD = 15 V
  • 5 V, 10 V and 15 V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices".
  • Applications
    • Rate comparators
    • General counting applications where display is desired
    • Up-down counting applications where input pulses are random in nature
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Description

CD40110B is a dual-clocked up/down counter with a special preconditioning circuit that allows the counter to be clocked, via positive going inputs, up or down regardless of the state or timing (within 100 ns typ.) of the other clock line.

The clock signal is fed into the control logic and Johnson counter after it is preconditioned. The outputs of the Johnson counter (which include anti-lock gating to avoid being locked at an illegal state) are fed into a latch. This data can be fed directly to the decoder through the latch or can be strobed to hold a particular count while the Johnson counter continues to be clocked. The decoder feeds a seven-segment bipolar output driver which can source up to 25 mA to drive LEDs and other displays such as low-voltage fluorescent and incandescent lamps.

A short durating negative-going pulse appears on the BORROW output when the count changes from 0 to 9 or the CARRY output when the count changes from 9 to 0. At the other times the BORROW and CARRY outputs are a logic 1.

The CARRY and BORROW outputs can be tied directly to the clock-up and clock-down lines respectively of another CD40110B for easy cascading of several counters.

The CD40110B types are supplied in 16-0lead dual-in-line ceramic packages (D and F suffixes), and 16-lead dual-in-line plastic package (E suffix), and also available in chip form, (H suffix).

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Technical documentation

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Type Title Date
* Data sheet CMOS Decade Up-Down Counter/Latch/Display Driver datasheet Nov. 21, 1998
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options

Ordering & quality

Information included:
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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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