Product details


Technology Family CD4000 Function Frequency divider Bits (#) 4 VCC (Min) (V) 3 VCC (Max) (V) 18 Input type Standard CMOS Output type Push-pull Data rate (Max) (Mbps) 7 ICC (Max) (uA) 3000 IOL (Max) (mA) 2.4 IOH (Max) (mA) -2.4 Features Standard speed (tpd > 50ns), Partial power down (Ioff) open-in-new Find other Rate multiplier/frequency divider/timer

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Rate multiplier/frequency divider/timer


  • Reset disables the RC oscillator for low-power standby condition
  • VDD’ and VSS’ pins are brought out from the crystal oscillator to allow use of external resistors for low-power operation
  • Maximum input current of 1 µA at 18 V over full package-temperature range:
    100 nA at 18 V and 25°C
  • Common reset
  • 100% tested for 20-V quiescent current
  • 5, 10 and 15 V parametric ratings
  • Standardized symmetrical output characteristics
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

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CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet CD4521B TYPES datasheet (Rev. C) Oct. 15, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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