Product details

Number of channels (#) 9 Technology Family AC Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode
Number of channels (#) 9 Technology Family AC Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode
PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6
  • Buffered Inputs
  • Typical Propagation Delay
    - 10ns at VCC = 5V, TA = 25°C, CL = 50pF
  • Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current
    - Fanout to 15 FAST™ ICs
    - Drives 50 Transmission Lines
  • Characterized for operation from –40° to 85°C

FAST™ is a Trademark of Fairchild Semiconductor.

  • Buffered Inputs
  • Typical Propagation Delay
    - 10ns at VCC = 5V, TA = 25°C, CL = 50pF
  • Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current
    - Fanout to 15 FAST™ ICs
    - Drives 50 Transmission Lines
  • Characterized for operation from –40° to 85°C

FAST™ is a Trademark of Fairchild Semiconductor.

The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional ’AC280, ’ACT280 parity checker.

The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional ’AC280, ’ACT280 parity checker.

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Technical documentation

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Type Title Date
* Data sheet 9-Bit Odd/Even Parity Generator/Checker datasheet (Rev. A) 17 May 2000
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

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