Product details

Technology Family AC Supply voltage (Min) (V) 1.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 24 ICC (Max) (uA) 160 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
Technology Family AC Supply voltage (Min) (V) 1.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 24 ICC (Max) (uA) 160 IOH (Max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DB) 20 38 mm² 5.3 x 7.2
  • Buffered inputs
  • Typical propagation delay:
    4.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST®/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST® ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

FAST is a Registered Trademark of Fairchild Semiconductor Corp.

  • Buffered inputs
  • Typical propagation delay:
    4.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST®/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST® ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The CD54/74AC540, –541, and CD54/74ACT540, –541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.

The CD74AC540, –541, and CD74ACT540, –541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).

The CD54AC540, –541, and CD54ACT540, –541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.

The CD54/74AC540, –541, and CD54/74ACT540, –541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.

The CD74AC540, –541, and CD74ACT540, –541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).

The CD54AC540, –541, and CD54ACT540, –541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.

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Technical documentation

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Type Title Date
* Data sheet Octal Buffer/Line Drivers, 3-State datasheet (Rev. A) 16 Nov 1999
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

Not available on TI.com
Simulation model

CD74AC541 IBIS Model CD74AC541 IBIS Model

Simulation model

CD74AC541 Behavioral SPICE Model CD74AC541 Behavioral SPICE Model

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options

Ordering & quality

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