CD74FCT843A

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BiCMOS FCT Interface Logic 9-Bit Non-Inverting Transparent Latches with 3-State Outputs

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Product details

Parameters

Technology Family FCT Input type TTL-Compatible CMOS Output type 3-State VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 9 Clock Frequency (Max) (MHz) 70 ICC (uA) 80 IOL (Max) (mA) 48 IOH (Max) (mA) -15 Features Very high speed (tpd 5-10ns), Partial power down (Ioff) Rating Catalog open-in-new Find other D-type latch

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other D-type latch

Features

  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Packaged in Plastic Small-Outline Package
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Description

The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE\) input controls the 3-state outputs. When OE\ is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE\) and clear (CLR\), are ideal for parity-bus interfacing. When PRE\ is low, the outputs are high if OE\ is low. PRE\ overrides CLR\. When CLR\ is low, the outputs are low if OE\ is low. When CLR\ is high, data can be entered into the latch. The device provides noninverted outputs.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Datasheet BiCMOS 9-Bit Bus-Interface D-Type Latch With 3-State Outputs datasheet Jul. 02, 2000
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

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