CD74HC4017-Q1

Name: CD74HC4017-Q1
Brand: TI
SKU: CD74HC4017-Q1
Price: 0.237 USD

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Automotive Catalog Decade Counter/Divider with 10 Decoded Outputs

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Data sheet

document-pdfAcrobat High-Speed CMOS Logic Decade Counter/Divider With 10 Decoded Outputs datasheet (Rev. A)

CD74HC4017-Q1

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Data sheet

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Product details

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

TSSOP (PW)

16

32 mm² 5 x 6.4

Qualified for Automotive Applications
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 60 MHz at V_CC = 5 V,
C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
V_CC Voltage = 2 V to 6 V
High Noise Immunity N_IL or N_IH = 30% of V_CC, V_CC = 5 V

Qualified for Automotive Applications
Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 60 MHz at V_CC = 5 V,
C_L = 15 pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . 10 LSTTL Loads
- Bus Driver Outputs . . . 15 LSTTL Loads
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
V_CC Voltage = 2 V to 6 V
High Noise Immunity N_IL or N_IH = 30% of V_CC, V_CC = 5 V

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

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