Product details

Configuration Universal Bits (#) 8 Technology Family FCT Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock Frequency (MHz) 70 IOL (Max) (mA) 64 IOH (Max) (mA) -32 ICC (Max) (uA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff)
Configuration Universal Bits (#) 8 Technology Family FCT Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock Frequency (MHz) 70 IOL (Max) (mA) 64 IOH (Max) (mA) -32 ICC (Max) (uA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff)
SOIC (DW) 24 160 mm² 15.5 x 10.3
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs

  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Other devices and data sheet

This data sheet applies to both  CY29FCT520T and  CY29FCT520T-MIL

Technical documentation

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Type Title Date
* Data sheet Multilevel Pipeline Register With 3-State Outputs datasheet (Rev. C) 02 Nov 2001
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide CYFCT Parameter Measurement Information 02 Apr 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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SOIC (DW) 24 View options

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