Product details

Power switch MOSFET, GaNFET Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 5.5 Peak output current (A) 5 Rise time (ns) 7 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 4 Rating Catalog Number of channels (#) 2 Fall time (ns) 3.5 Prop delay (ns) 35 Iq (uA) 90 Input threshold TTL Channel input logic TTL Negative voltage handling at HS pin (V) -5 Features Bootstrap supply voltage clamping, Split outputs on high and low side
Power switch MOSFET, GaNFET Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 5.5 Peak output current (A) 5 Rise time (ns) 7 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 4 Rating Catalog Number of channels (#) 2 Fall time (ns) 3.5 Prop delay (ns) 35 Iq (uA) 90 Input threshold TTL Channel input logic TTL Negative voltage handling at HS pin (V) -5 Features Bootstrap supply voltage clamping, Split outputs on high and low side
DSBGA (YFX) 12 0 mm² 1.765 x 1.915
  • Independent High-Side and Low-Side
    TTL Logic Inputs
  • 1.2-A Peak Source, 5-A Sink Current
  • High-Side Floating Bias Voltage Rail
    Operates up to 100 VDC
  • Internal Bootstrap Supply Voltage Clamping
  • Split Outputs for Adjustable
    Turnon, Turnoff Strength
  • 0.6-Ω Pulldown, 2.1-Ω Pullup Resistance
  • Fast Propagation Times (35 ns Typical)
  • Excellent Propagation Delay Matching
    (1.5 ns Typical)
  • Supply Rail Undervoltage Lockout
  • Low Power Consumption
  • Independent High-Side and Low-Side
    TTL Logic Inputs
  • 1.2-A Peak Source, 5-A Sink Current
  • High-Side Floating Bias Voltage Rail
    Operates up to 100 VDC
  • Internal Bootstrap Supply Voltage Clamping
  • Split Outputs for Adjustable
    Turnon, Turnoff Strength
  • 0.6-Ω Pulldown, 2.1-Ω Pullup Resistance
  • Fast Propagation Times (35 ns Typical)
  • Excellent Propagation Delay Matching
    (1.5 ns Typical)
  • Supply Rail Undervoltage Lockout
  • Low Power Consumption

The LMG1205 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or half-bridge configuration. The device has an integrated 100-V bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LMG1205 are TTL logic compatible and can withstand input voltages up to 14 V regardless of the VDD voltage. The LMG1205 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently.

In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching. The LMG1205 can operate up to several MHz. The LMG1205 is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance.

The LMG1205 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or half-bridge configuration. The device has an integrated 100-V bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LMG1205 are TTL logic compatible and can withstand input voltages up to 14 V regardless of the VDD voltage. The LMG1205 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently.

In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching. The LMG1205 can operate up to several MHz. The LMG1205 is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance.

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Technical documentation

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Type Title Date
* Data sheet LMG1205 80-V, 1.2-A to 5-A, Half Bridge GaN Driver with Integrated Bootstrap Diode datasheet (Rev. A) 27 Feb 2018
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
White paper Optimizing multi-megahertz GaN driver design white paper (Rev. A) 27 Nov 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018
User guide Using the LMG1205HBEVM 22 Mar 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMG1205HBEVM — LMG1205 GaN Power Stage Evaluation Module

80-V 10A Power Stage EVM - The LMG1205 half-bridge EVM board is a small, easy to use, power stage with an external PWM signal. The EVM is suitable for evaluating the performance of the LMG1205 driving a GaN half-bridge in many different DC-DC converter topologies. It can be used to estimate the (...)

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Simulation model

LMG1205 TINA-TI Transient Spice Model (Rev. A)

SNOM621A.ZIP (9 KB) - TINA-TI Spice Model
Simulation model

LMG1205 TINA-TI Reference Design (Rev. A)

SNOM622A.TSC (131 KB) - TINA-TI Reference Design
Simulation model

LMG1205 PSpice Transient Model (Rev. A)

SNOM624A.ZIP (35 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

PMP22519 — Unregulated LLC module reference design for two-stage 54-V POL in data centers

This reference design is for two-stage power architecture for 54V to VCore voltage regulator module (VRM) powering CPUs, GPUs and DDR memory in 48-V rack power architecture in data centers. The First-stage is an unregulated LLC resonant converter with an integrated planar magnetic structure and (...)
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DSBGA (YFX) 12 View options

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