SN54HC374

ACTIVE

Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs

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Product details

Parameters

Number of channels (#) 8 Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 25 IOL (Max) (mA) 7.8 IOH (Max) (mA) -7.8 ICC (Max) (uA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other D-type flip-flop

Package | Pins | Size

CDIP (J) 20 167 mm² 26.92 x 7.62 CFP (W) 20 91 mm² 13 x 7 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other D-type flip-flop

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State True Outputs Can
    Drive Up To 15 LSTTL Loads
  • Eight D-Type Flip-Flops in a Single Package
  • Full Parallel Access for Loading
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

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Description

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the \x92HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.

An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet SN54HC374, SN74HC374 datasheet (Rev. E) Aug. 19, 2003
* SMD SN54HC374 SMD 84071012A Jun. 21, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 20 View options
CFP (W) 20 View options
LCCC (FK) 20 View options

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