SN54LS175

ACTIVE

Quadruple D-type Flip-Flops With Clear

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Product details

Parameters

Channels (#) 4 Technology Family LS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock Frequency (Max) (MHz) 35 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 ICC (Max) (uA) 18000 Features High speed (tpd 10-50ns) open-in-new Find other D-type flip-flop

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 CFP (W) 16 69 mm² 10 x 6.7 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other D-type flip-flop

Features

  • '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
  • '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
  • Three Performance Ranges Offered: See Table Lower Right
  • Buffered Clock and Direct Clear Inputs
  • Individual Data Input to Each Flip-Flop
  • Applications include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

open-in-new Find other D-type flip-flop

Description

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

open-in-new Find other D-type flip-flop
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Technical documentation

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Type Title Date
* Datasheet Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. A) Oct. 12, 2001
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
CFP (W) 16 View options
LCCC (FK) 20 View options

Ordering & quality

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