SN65DSI84

ACTIVE

MIPI® DSI bridge to Flatlink™ LVDS single-channel DSI to dual-link LVDS bridge

Product details

Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 4 Operating temperature range (°C) -40 to 85
Type Bridge Protocols LVDS, MIPI DSI Rating Catalog Speed (max) (Gbpp) 4 Operating temperature range (°C) -40 to 85
NFBGA (ZXH) 64 25 mm² (5 mm × 5 mm)
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60-fps WUXGA 1920 × 1200 resolution at 18-bpp and 24-bpp color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports single channel DSI to dual-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60-fps WUXGA 1920 × 1200 resolution at 18-bpp and 24-bpp color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports single channel DSI to dual-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C.

The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.

The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet MIPI DSI Bridge to Flat Link LVDS Single Channel DSI to Dual-Link LVDS Bridge datasheet (Rev. H) PDF | HTML Nov 11, 2020
Application note Troubleshooting SN65DSI8x - Tips and Tricks Aug 27, 2018
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) Apr 11, 2013
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) Apr 8, 2013

Design & development

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Evaluation board

SN65DSI85EVM — SN65DSI85 dual-channel MIPI® DSI to dual-link FlatLink™ LVDS bridge evaluation module

The SN65DSI85EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implementthe SN65DSI85 device in system hardware. This EVM can be used as a hardware reference design for any implementation using the SN65DSI85 device. The SN65DSI85EVM includes (...)
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IDE, configuration, compiler or debugger

DSI-TUNER — Tuner video configuration software tool

The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)

Supported products & hardware
Simulation model

SN65DSI84 IBIS Model

SLLM203.ZIP (254 KB) - IBIS model
Supported products & hardware
Simulation model

SN65DSI85 Hspice Model

SLLJ007.ZIP (1092 KB) - HSpice model
Supported products & hardware
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NFBGA (ZXH) 64 Ultra Librarian

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