Product details

Protocols LVDS, MIPI DSI Speed (Max) (Gbps) 8 Supply voltage (V) 1.8 Operating temperature range (C) -40 to 85
Protocols LVDS, MIPI DSI Speed (Max) (Gbps) 8 Supply voltage (V) 1.8 Operating temperature range (C) -40 to 85
NFBGA (ZXH) 64 25 mm² 5 x 5
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps WQXGA 2560 × 1600 resolution at 18-bpp and 24-bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI® front-end configurable for single-channel or dual-channel DSI configurations
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
  • Supports two single-channel DSI to two single-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low-power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI® ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS pin order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm x 5 mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C
  • Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
  • Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
  • Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
  • Suitable for 60 fps WQXGA 2560 × 1600 resolution at 18-bpp and 24-bpp color, and WUXGA 1920 × 1200 resolution with 3D graphics at 60 fps (120 fps equivalent)
  • MIPI® front-end configurable for single-channel or dual-channel DSI configurations
  • FlatLink™ output configurable for single-link or dual-link LVDS
  • Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
  • Supports two single-channel DSI to two single-link LVDS operating mode
  • LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
  • LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
  • 1.8-V main VCC power supply
  • Low-power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI® ultra-low power state (ULPS) support
  • LVDS channel swap, LVDS pin order reverse feature for ease of PCB routing
  • ESD rating ±2 kV (HBM)
  • Packaged in 64-pin 5 mm x 5 mm nFBGA (ZXH)
  • Temperature range: –40°C to 85°C

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.

The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.

The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet SN65DSI85 MIPI® DSI Bridge to FlatLink LVDS Dual Channel DSI to Dual-Link LVDS datasheet (Rev. G) 01 Oct 2020
Application note Troubleshooting SN65DSI8x - Tips and Tricks 27 Aug 2018
EVM User's guide SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide 17 Nov 2015
Application note SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) 11 Apr 2013
Application note SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) 08 Apr 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SN65DSI85EVM — SN65DSI85 dual-channel MIPI® DSI to dual-link FlatLink™ LVDS bridge evaluation module

The SN65DSI85EVM evaluation module (EVM) is a printed circuit board (PCB) that helps customers implementthe SN65DSI85 device in system hardware. This EVM can be used as a hardware reference design for any implementation using the SN65DSI85 device. The SN65DSI85EVM includes (...)
User guide: PDF
Not available on TI.com
IDE, configuration, compiler or debugger

DSI-TUNER — Tuner video configuration software tool

The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)
Simulation model

SN65DSI85 Hspice Model

SLLJ007.ZIP (1092 KB) - HSpice Model
Simulation model

SN65DSI85 IBIS Model (Rev. A)

SLLM201A.ZIP (159 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
NFBGA (ZXH) 64 View options

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