The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.
The SN65DSI85 is well suited for WQXGA (2560 × 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI85 is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN65DSI85 MIPI® DSI Bridge to FlatLink LVDS Dual Channel DSI to Dual-Link LVDS datasheet (Rev. G) | PDF | HTML | Oct 1, 2020 |
| Application note | Troubleshooting SN65DSI8x - Tips and Tricks | Aug 27, 2018 | ||
| Application note | SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A) | Apr 11, 2013 | ||
| Application note | SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B) | Apr 8, 2013 |
For additional terms or required resources, click any title below to view the detail page where available.
The DSI Tuner video configuration tool generates the video timing and the configuration register values required to transfer the DSI data to the LVDS panel using the SN65DSI8x DSI-to-LVDS bridge device. The timing and the register values are calculated based on inputs entered in the input fields (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| NFBGA (ZXH) | 64 | Ultra Librarian |
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.