3.3V Differential Transceiver
Product details
Parameters
Package | Pins | Size
Features
- Operates With a 3.3-V Supply
- Bus-Pin ESD Protection Exceeds 16-kV HBM
- 1/8 Unit-Load Option Available (Up to 256 Nodes on the Bus)
- Optional Driver Output Transition Times for Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps - Meets or Exceeds the Requirements of ANSI TIA/EIA-485-A
- Bus-Pin Short-Circuit Protection From –7 V to
12 V - Low-Current Standby Mode: 1 µA, Typical
- Open-Circuit, Idle-Bus, and Shorted-Bus Failsafe Receiver
- Thermal Shutdown Protection
- Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications
- SN75176 Footprint
(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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Description
The SN65HVD10, SN75HVD10, SN65HVD11, SN75HVD11, SN65HVD12, and SN75HVD12 bus transceivers combine a 3-state differential line driver and differential input line receiver that operate with a single 3.3-V power supply. They are designed for balanced transmission lines and meet or exceed ANSI standard TIA/EIA-485-A and ISO 8482:1993. These differential bus transceivers are monolithic integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. The drivers and receivers have active-high and active-low enables, respectively, that can be externally connected together to function as direction control. Very low device standby supply current can be achieved by disabling the driver and the receiver.
The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These parts feature wide positive and negative common-mode voltage ranges making them suitable for party-line applications.
Same functionality and pinout but is not an equivalent to the compared device:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SNx5HVD1x 3.3-V RS-485 Transceivers datasheet (Rev. O) | Feb. 01, 2017 |
User guide | RS-485 Half-Duplex EVM User's Guide (Rev. B) | Jun. 12, 2013 | |
Application note | Device spacing on RS-485 buses | Apr. 18, 2006 | |
Application note | The RS-485 Unit Load and Maximum Number of Bus Connections | Mar. 15, 2004 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
The EVM lets you quickly, easily and accurately evaluate TI's family of RS-485 products.
Hardware:- RS-485 half-duplex EVM PWB
- Screw-type SMA jacks and Bergstik headers serve as the I/O connections
- Banana jacks serve as the DC power input terminals
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
PDIP (P) | 8 | View options |
SOIC (D) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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