SN74ABT162823A

ACTIVE

18-Bit Bus-Interface Flip-Flops With 3-State Outputs

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18-Bit Bus-Interface Flip-Flops With 3-State Outputs

SN74ABT162823A

ACTIVE

Product details

Parameters

Channels (#) 18 Technology Family ABT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 150 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Power up 3-state, Damping resistors open-in-new Find other D-type flip-flop

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 open-in-new Find other D-type flip-flop

Features

  • Members of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 25- Series Resistors So No External Resistors Are Required
  • Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout

Widebus is a trademark of Texas Instruments.

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Description

These 18-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ’ABT162823A devices can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN)\ input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR)\ input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE)\ input places the nine outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN54ABT162823A, SN74ABT162823A datasheet (Rev. B) Jun. 08, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application notes Quad Flatpack No-Lead Logic Packages (Rev. D) Feb. 16, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) Mar. 01, 1997
Application notes Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

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SSOP (DL) 56 View options

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